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参数资料
| 型号： | AD7739BRU-REEL |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 8-Channel, High Throughput, 24-Bit Sigma-Delta ADC |
| 中文描述： | 8-CH 24-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封装： | MS-153AD, TSSOP-24 |
| 文件页数： | 6/32页 |
| 文件大小： | 380K |
| 代理商： | AD7739BRU-REEL |
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AD7739
TIMING SPECIFICATIONS
Table 2. (AV
DD
= 5 V ± 5%; DV
DD
= 2.7 V to 3.6 V, or 5 V ± 5%; Input Logic 0 = 0 V; Logic 1 = DV
DD
;
unless otherwise noted.)
1
Parameter
Min
Typ
Max
Master Clock Range
1
6.144
1
4
t
1
50
t
2
500
Read Operation
t
4
0
t
52
0
60
0
80
t
5A2, 3
0
60
0
80
t
6
50
t
7
50
t
8
0
t
94
10
80
Write Operation
t
11
0
t
12
30
t
13
25
t
14
50
t
15
50
t
16
0
Rev. 0 | Page 6 of 32
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
Reduced Power Mode
SYNC Pulsewidth
RESET Pulsewidth
CS Falling Edge to SCLK Falling Edge Setup Time
SCLK Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
CS Falling Edge to Data Valid Delay
DV
DD
of 4.75 V to 5.25 V
DV
DD
of 2.7 V to 3.3 V
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
Bus Relinquish Time after SCLK Rising Edge
CS Falling Edge to SCLK Falling Edge Setup
Data Valid to SCLK Rising Edge Setup Time
Data Valid after SCLK Rising Edge Hold Time
SCLK High Pulsewidth
SCLK Low Pulsewidth
CS Rising Edge after SCLK Rising Edge Hold Time
1
Sample tested during initial release to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of DV
DD
) and timed from a voltage level of
1.6 V. See Figure 2 and Figure 3.
2
These numbers are measured with the load circuit of Figure 4 and defined as the time required for the output to cross the V
OL
or V
OH
limits.
3
This specification is relevant only if CS goes low while SCLK is low.
4
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 4. The measured number is then
extrapolated back to remove effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the Timing Specifications are the true bus
relinquish times of the part and as such are independent of external bus loading capacitances.
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