- 您现在的位置：买卖IC网 > PDF目录10681 > AD7791BRMZ (Analog Devices Inc)IC ADC 24BIT BUFFERED LP 10MSOP PDF资料下载
参数资料
| 型号： | AD7791BRMZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC ADC 24BIT BUFFERED LP 10MSOP |
| 标准包装： | 50 |
| 位数： | 24 |
| 采样率（每秒）： | 120 |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 230µW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极；1 个差分，双极 |
| 产品目录页面： | 779 (CN2011-ZH PDF) |
Data Sheet
AD7791
Rev. A | Page 5 of 20
TIMING CHARACTERISTICS1, 2
Table 2. (VDD = 2.5 V to 5.25 V; GND = 0 V, REFIN(+) = 2.5 V, REFIN(–) = GND, CDIV1 = CDIV0 = 0, Input Logic 0 = 0 V,
Input Logic 1 = VDD, unless otherwise noted.)
Parameter
Limit at TMIN, TMAX
(B Version)
Unit
Conditions/Comments
t3
100
ns min
SCLK High Pulsewidth
t4
100
ns min
SCLK Low Pulsewidth
Read Operation
t1
0
ns min
CS Falling Edge to DOUT/RDY Active Time
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.5 V to 3.6 V
t23
0
ns min
SCLK Active Edge to Data Valid Delay4
60
ns max
VDD = 4.75 V to 5.25 V
80
ns max
VDD = 2.5 V to 3.6 V
10
ns min
Bus Relinquish Time after CS Inactive Edge
80
ns max
t6
100
ns max
SCLK Inactive Edge to CS Inactive Edge
t7
10
ns min
SCLK Inactive Edge to DOUT/RDY High
Write Operation
t8
0
ns min
CS Falling Edge to SCLK Active Edge Setup Time4
t9
30
ns min
Data Valid to SCLK Edge Setup Time
t10
25
ns min
Data Valid to SCLK Edge Hold Time
t11
0
ns min
CS Rising Edge to SCLK Edge Hold Time
1
Sample tested during initial release to ensure compliance. All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
2
3
These numbers are measured with the load circuit of Figure 2 and defined as the time required for the output to cross the VOL or VOH limits.
4
SCLK active edge is falling edge of SCLK.
5
These numbers are derived from the measured time taken by the data output to change 0.5 V when loaded with the circuit of Figure 2. The measured number is then
extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the times quoted in the timing characteristics are the true bus
relinquish times of the part and, as such, are independent of external bus loading capacitances.
6
RDY returns high after a read of the ADC. In single conversion mode and continuous conversion mode, the same data can be read again, if required, while RDY is high,
although care should be taken to ensure that subsequent reads do not occur close to the next output update. In continuous read mode, the digital word can be read
only once.
相关PDF资料 |
PDF描述 |
|---|---|
| VI-22Z-MY-B1 | CONVERTER MOD DC/DC 2V 20W |
| CS5529-ASZ | IC ADC 16BIT W/6BIT LATCH 20SSOP |
| VI-22Z-MW-B1 | CONVERTER MOD DC/DC 2V 40W |
| AD7798BRUZ | IC ADC 16BIT SIG-DEL 3CH 16TSSOP |
| VI-22T-MY-B1 | CONVERTER MOD DC/DC 6.5V 50W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD7791BRMZ | 制造商:Analog Devices 功能描述:IC 16BIT ADC SMD 7791 MSOP10 |
| AD7791BRMZ-REEL | 功能描述:IC ADC 24BIT SIGMA-DELTA 10MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
| AD7792 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power, 16/24-Bit Sigma-Delta ADC with Low-Noise In-Amp and Embedded Reference |
| AD7792_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:3-Channel, Low Noise, Low Power, 16-/24-Bit ?￡-?? ADC with On-Chip In-Amp and Reference |
| AD7792BRU | 功能描述:IC ADC 16BIT 3CH LP 16-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:16 采样率（每秒）:45k 数据接口:串行 转换器数目:2 功率耗散（最大）:315mW 电压电源:模拟和数字 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-SOIC（0.295"，7.50mm 宽） 供应商设备封装:28-SOIC W 包装:带卷 (TR) 输入数目和类型:2 个单端，单极 |
发布紧急采购，3分钟左右您将得到回复。