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| 型号： | AD7811YRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 4CHAN SRL 16-TSSOP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 标准包装： | 2,500 |
| 位数： | 10 |
| 采样率（每秒）： | 350k |
| 数据接口： | DSP，串行 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 10.5mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 4 个单端，单极；3 个伪差分，单极 |
AD7811/AD7812
–10–
REV. B
CIRCUIT DESCRIPTION
Converter Operation
The AD7811 and AD7812 are successive approximation analog-
to-digital converters based around a charge redistribution DAC.
The ADCs can convert analog input signals in the range 0 V to
VDD. Figures 2 and 3 show simplified schematics of the ADC.
Figure 2 shows the ADC during its acquisition phase. SW2 is
closed and SW1 is in position A, the comparator is held in a
balanced condition and the sampling capacitor acquires the
signal on VIN.
VIN
VDD/3
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
ACQUISITION
PHASE
SW1
A
B
SW2
AGND
SAMPLING
CAPACITOR
CHARGE
REDISTRIBUTION
DAC
Figure 2. ADC Acquisition Phase
When the ADC starts a conversion, see Figure 3, SW2 will
open and SW1 will move to position B causing the comparator
to become unbalanced. The Control Logic and the Charge
Redistribution DAC are used to add and subtract fixed amounts
of charge from the sampling capacitor to bring the comparator
back into a balanced condition. When the comparator is rebal-
anced, the conversion is complete. The Control Logic generates
the ADC output code. Figure 10 shows the ADC transfer
function.
VIN
VDD/3
COMPARATOR
CONTROL
LOGIC
CLOCK
OSC
CONVERSION
PHASE
SW1
A
B
SW2
SAMPLING
CAPACITOR
AGND
CHARGE
REDISTRIBUTION
DAC
Figure 3. ADC Conversion Phase
TYPICAL CONNECTION DIAGRAM
Figure 4 shows a typical connection diagram for the AD7811/
AD7812. The AGND and DGND are connected together at
the device for good noise suppression. The serial interface is
implemented using three wires with RFS/TFS connected to
CONVST see Serial Interface section for more details. V
REF is
connected to a well decoupled VDD pin to provide an analog
input range of 0 V to VDD. If the AD7811 or AD7812 is not
sharing a serial bus with another AD7811 or AD7812 then A0
(package address pin) should be hardwired low. The default
power up value of the package address bit in the control register
is 0. For applications where power consumption is of concern,
the automatic power down at the end of a conversion should be
used to improve power performance. See Power-Down Options
section of the data sheet.
SUPPLY
2.7V TO 5.5V
10 F
C/P
THREE-WIRE
SERIAL
INTERFACE
10nF
VREF
DIN
SCLK
CONVST
VDD
CREF
VIN1
AGND
TFS
RFS
DOUT
A0
DGND
0.1 F
VIN2
VIN4(8)
AD7811/
AD7812
0V TO
VREF
INPUT
Figure 4. Typical Connection Diagram
Analog Input
Figure 5 shows an equivalent circuit of the analog input struc-
ture of the AD7811 and AD7812. The two diodes D1 and D2
provide ESD protection for the analog inputs. Care must be
taken to ensure that the analog input signal never exceeds the
supply rails by more than 200 mV. This will cause these diodes
to become forward biased and start conducting current into
the substrate. 20 mA is the maximum current these diodes can
conduct without causing irreversible damage to the part. How-
ever, it is worth noting that a small amount of current (1 mA)
being conducted into the substrate due to an overvoltage on an
unselected channel can cause inaccurate conversions on a
selected channel. The capacitor C2 in Figure 5 is typically about
4 pF and can primarily be attributed to pin capacitance. The
resistor R1 is a lumped component made up of the on resistance
of a multiplexer and a switch. This resistor is typically about
125
. The capacitor C1 is the ADC sampling capacitor and
has a capacitance of 3.5 pF.
CONVERSION PHASE – SWITCH OPEN
TRACK PHASE – SWITCH CLOSED
VIN
D1
D2
VDD /3
C1
3.5pF
R1
125
C2
4pF
VDD
Figure 5. Equivalent Analog Input Circuit
The analog inputs on the AD7811 and AD7812 can be config-
ured as single ended with respect to analog ground (AGND),
as pseudo differential with respect to a common, and also as
pseudo differential pairs—see Control Register section.
C
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