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参数资料
| 型号： | AD7859LASZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT 8CHAN LP 44-MQFP |
| 标准包装： | 800 |
| 位数： | 12 |
| 采样率（每秒）： | 100k |
| 数据接口： | 并联 |
| 转换器数目： | 2 |
| 功率耗散（最大）： | 30mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-QFP |
| 供应商设备封装： | 44-MQFP（10x10） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 8 个单端，单极；8 个单端，双极；4 个伪差分，单极；4 个伪差分，双极 |
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AD7859/AD7859L
REV. A
–21–
CALIBRATION SECTION
Calibration Overview
The automatic calibration that is performed on power-up
ensures that the calibration options covered in this section are
not required in a significant number of applications. A calibra-
tion does not have to be initiated unless the operating condi-
tions change (CLKIN frequency, analog input mode, reference
voltage, temperature, and supply voltages). The AD7859/
AD7859L has a number of calibration features that may be
required in some applications, and there are a number of advan-
tages in performing these different types of calibration. First, the
internal errors in the ADC can be reduced significantly to give
superior dc performance; and second, system offset and gain er-
rors can be removed. This allows the user to remove reference
errors (whether it be internal or external reference) and to make
use of the full dynamic range of the AD7859/AD7859L by ad-
justing the analog input range of the part for a specific system.
There are two main calibration modes on the AD7859/AD7859L,
self-calibration and system calibration. There are various op-
tions in both self-calibration and system calibration as outlined
previously in Table IV. All the calibration functions are initi-
ated by writing to the control register and setting the STCAL
bit to 1.
The duration of each of the different types of calibration is given
in Table IX for the AD7859 with a 4 MHz master clock. These
calibration times are master clock dependent. Therefore the
calibration times for the AD7859L (CLKIN = 1.8 MHz) are
larger than those quoted in Table IX.
Table IX. Calibration Times (AD7859 with 4 MHz CLKIN)
Type of Self-Calibration or System Calibration
Time
Full
31.25 ms
Gain + Offset
6.94 ms
Offset
3.47 ms
Gain
3.47 ms
Calibration on Power-On
The calibration on power-on is initiated by the first CONVST
pulse after the AVDD and DVDD power on. From the CONVST
pulse the part internally sets a 32/72 ms (4 MHz/1.8 MHz
CLKIN) timeout. This time is large enough to ensure that the
internal reference has settled before the calibration is performed.
However, if an external reference is being used, this reference
must have stabilized before the automatic calibration is initiated.
This first CONVST pulse also triggers the BUSY signal high,
and once the 32/72 ms has elapsed, the BUSY signal goes low.
At this point the next CONVST pulse that is applied initiates
the automatic full self-calibration. This CONVST pulse again
triggers the BUSY signal high, and after 32/72 ms (4 MHz/
1.8 MHz CLKIN), the calibration is completed and the BUSY
signal goes low. This timing arrangement is shown in Figure 28.
The times in Figure 28 assume a 4 MHz/1.8 MHz CLKIN signal.
AVDD = DVDD
CONVST
BUSY
POWER-ON
32/72ms
TIMEOUT PERIOD
AUTOMATIC
CALIBRATION
DURATION
CONVERSION IS INITIATED
ON THIS EDGE
Figure 28. Timing Arrangement for Autocalibration on
Power-On
The CONVST signal is gated with the BUSY internally so that
as soon as the timeout is initiated by the first CONVST pulse all
subsequent CONVST pulses are ignored until the BUSY signal
goes low, 32/72 ms later. The CONVST pulse that follows after
the BUSY signal goes low initiates a full self-calibration. This
takes a further 32/72 ms. After calibration, the part is accurate
to the 12-bit level and the specifications quoted on the data
sheet apply; all subsequent CONVST pulses initiate conver-
sions. There is no need to perform another calibration unless
the operating conditions change or unless a system calibration is
required.
This autocalibration at power-on is disabled if the user writes to
the control register before the autocalibration is initiated. If the
control register write operation occurs during the first 32/72 ms
timeout period, then the BUSY signal stays high for the 32/72
ms and the CONVST pulse that follows the BUSY going low
does not initiate a full self-calibration. It initiates a conversion
and all subsequent CONVST pulses initiate conversions as well.
If the control register write operation occurs when the automatic
full self-calibration is in progress, then the calibration is not be
aborted; the BUSY signal remains high until the automatic full
self-calibration is complete.
Self-Calibration Description
There are four different calibration options within the self-
calibration mode. There is a full self-calibration where the
DAC, internal offset, and internal gain errors are removed.
There is the (Gain + Offset) self-calibration which removes the
internal gain error and then the internal offset errors. The inter-
nal DAC is not calibrated here. Finally, there are the self-offset
and self-gain calibrations which remove the internal offset errors
and the internal gain errors respectively.
The internal capacitor DAC is calibrated by trimming each of
the capacitors in the DAC. It is the ratio of these capacitors to
each other that is critical, and so the calibration algorithm en-
sures that this ratio is at a specific value by the end of the cali-
bration routine. For the offset and gain there are two separate
capacitors, one of which is trimmed during offset calibration
and one of which is trimmed during gain calibration.
In Bipolar Mode the midscale error is adjusted by an offset cali-
bration and the positive full-scale error is adjusted by the gain
calibration. In Unipolar Mode the zero-scale error is adjusted
by the offset calibration and the positive full-scale error is ad-
justed by the gain calibration.
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