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参数资料
| 型号： | AD7912AUJZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT DUAL 2CH TSOT-23-8 |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 20mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 标准包装 |
| 输入数目和类型： | 2 个单端，单极 |
| 其它名称： | AD7912AUJZ-REEL7DKR |
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AD7912/AD7922
Rev. 0 | Page 24 of 32
POWER VS. THROUGHPUT RATE
By using the power-down mode on the AD7912/AD7922 when
not converting, the average power consumption of the ADC
decreases at lower throughput rates. Figure 36 shows how, as the
throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over
time drops.
For example, if the AD7912/AD7922 are operating in a continu-
ous sampling mode with a throughput rate of 100 kSPS and a
SCLK of 18 MHz (VDD = 5 V), and the devices are placed in the
power-down mode between conversions, then the power
consumption is calculated as follows. The power dissipation
during normal operation is 20 mW (VDD = 5 V). If the power-up
time is one dummy cycle (1 s), and the remaining conversion
time is another cycle (1 s), then the AD7912/AD7922 dissipate
20 mW for 2 s during each conversion cycle. If the throughput
rate is 100 kSPS and the cycle time is 10 s, then the average
power dissipated during each cycle is
(2/10) × (20 mW) = 4 mW
If VDD = 3 V, SCLK = 18 MHz, and the device is again in power-
down mode between conversions, then the power dissipation
during normal operation is 6 mW. The AD7912/AD7922 now
dissipate 6 mW for 2 s during each conversion cycle. With a
throughput rate of 100 kSPS, the average power dissipated
during each cycle is
(2/10) × (6 mW) = 1.2 mW
In the previous calculations, the power dissipation when the
part is in power-down mode has not been taken into account.
By placing the parts into power-down mode between conver-
sions, the average power consumed by the ADC decreases as
the throughput rate decreases, because the ADC remains in a
power-down state for a longer time.
Figure 36 shows the power consumption versus throughput rate
when using the power-down mode between conversions with
both 5 V and 3 V supplies.
Power-down mode is intended for use with throughput rates of
approximately 330 kSPS and under, because at higher sampling
rates the short time spent in power-down does not affect the
average power consumed by the ADC.
100
0.01
0.1
1
10
0
50
100
150
200
250
300
350
04351-0-033
THROUGHPUT (kSPS)
POW
ER
(
m
W
)
VDD = 5V, SCLK = 18MHz
VDD = 3V, SCLK = 18MHz
Figure 36. Power Consumption vs. Throughput Rate
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