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参数资料
| 型号： | AD7912AUJZ-REEL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 30/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT DUAL 2CH TSOT-23-8 |
| 标准包装： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 20mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | SOT-23-8 薄型，TSOT-23-8 |
| 供应商设备封装： | TSOT-23-8 |
| 包装： | 标准包装 |
| 输入数目和类型： | 2 个单端，单极 |
| 其它名称： | AD7912AUJZ-REEL7DKR |
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AD7912/AD7922
Rev. 0 | Page 7 of 32
TIMING SPECIFICATIONS
Guaranteed by characterization.
All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage level of 1.6 V.
VDD = 2.35 V to 5.25 V; TA = TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Limit at TMIN,
TMAX
Unit
Description
10
kHz min2
18
MHz max
tCONVERT
16 × tSCLK
AD7922
14 × tSCLK
AD7912
tQUIET
30
ns min
Minimum quiet time required between bus relinquish and start of next conversion
t1
15
ns min
Minimum CS pulse width
t2
10
ns min
CS to SCLK setup time
t33
30
ns max
Delay from CS until DOUT three-state is disabled
t43
45
ns max
DOUT access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK low pulse width
t6
0.4 tSCLK
ns min
SCLK high pulse width
t74
10
ns min
SCLK to DOUT valid hold time
t8
5
ns min
DIN setup time prior to SCLK falling edge
t9
6
ns min
DIN hold time after SCLK falling edge
t105
30
ns max
SCLK falling edge to DOUT three-state
10
ns min
SCLK falling edge to DOUT three-state
tPOWER-UP6
1
s max
Power-up time from full power-down
1 Mark/space ratio for SCLK input is 40/60 to 60/40.
2 Minimum fSCLK at which specifications are guaranteed.
3 Measured with the load circuit in Figure 2 and defined as the time required for the output to cross VIH or VIL voltage.
4 Measured with a 50 pF load capacitor.
5 T10 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 2. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t10, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
6 See the Power-Up Time section.
TIMING DIAGRAMS
04351-0-002
200
AI
OL
200
AI
OH
1.6V
TO OUTPUT
PIN
CL
50pF
Figure 2. Load Circuit for Digital Output Timing Specifications
04351-0-003
SCLK
VIH
VIL
DOUT
t4
Figure 3. Access Time after SCLK Falling Edge
04351-0-004
SCLK
VIH
VIL
DOUT
t7
Figure 4. Hold Time after SCLK Falling Edge
04351-0-005
SCLK
1.6V
DOUT
t10
Figure 5. SCLK Falling Edge to DOUT Three-State
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