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参数资料
| 型号： | AD7942BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 250KSPS 10-LFCSP |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 14 |
| 采样率（每秒）： | 250k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-WFDFN 裸露焊盘，CSP |
| 供应商设备封装： | 10-LFCSP-WD（3x3） |
| 包装： | 标准包装 |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7942CB-ND - BOARD EVALUATION FOR AD7942 |
| 其它名称： | AD7942BCPZRL7DKR |
AD7942
Rev. B | Page 20 of 2
4
CS Mode 4-Wire with Busy Indicator
This mode is most often used when a single AD7942 is
connected to an SPI-compatible digital host with an interrupt
input and to keep CNV (which is used to sample the analog
input) independent of the signal used to select the data reading.
This requirement is particularly important in applications where
low jitter on CNV is desired. The connection diagram is shown
in Figure 36 and the corresponding timing diagram is given in
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and held low until the maximum conversion time
is completed to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low. With a pull-up on the SDO line this
transition can be used as an interrupt signal to initiate the data
readback controlled by the digital host. The AD7942 then enters
the acquisition phase and powers down. The data bits are then
clocked out, MSB first, by subsequent SCK driving edges. The
data is valid on both SCK edges. Although the rising edge can
be used to capture the data, a digital host also using the SCK
falling edge allows a faster reading rate, provided it has an
acceptable hold time. After the optional 15th SCK falling edge
or SDI going high, whichever is earlier, the SDO returns to high
impedance.
CNV
SCK
SDO
SDI
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
AD7942
04
65
7-
03
6
47
Figure 36. CS Mode 4-Wire with Busy Indicator Connection Diagram
SDO
D13
D12
D1
D0
tDIS
SCK
1
2
3
131415
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
04
65
7-
03
7
Figure 37. CS Mode 4-Wire with Busy Indicator, Serial Interface Timing
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相关代理商/技术参数 |
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| AD7942BCPZRL71 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR, Pseudo Differential ADC in MSOP/QFN |
| AD7942BRM | 制造商:Analog Devices 功能描述:ADC Single SAR 250ksps 14-bit Serial 10-Pin MSOP Tube 制造商:Analog Devices 功能描述:IC 14-BIT ADC |
| AD7942BRMRL7 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 250 kSPS PulSAR ADC in MSOP/QFN |
| AD7942BRM-RL7 | 制造商:Analog Devices 功能描述:ADC Single SAR 250ksps 14-bit Serial 10-Pin MSOP T/R |
| AD7942BRMZ | 功能描述:IC ADC 14BIT 250KSPS 10-MSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:PulSAR® 标准包装:1 系列:microPOWER™ 位数:8 采样率（每秒）:1M 数据接口:串行，SPI? 转换器数目:1 功率耗散（最大）:- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘（4x4） 包装:Digi-Reel® 输入数目和类型:8 个单端，单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6 |
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