参数资料
| 型号： | AD7942BRMZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 250KSPS 10-MSOP |
| 标准包装： | 1,000 |
| 系列： | PulSAR® |
| 位数： | 14 |
| 采样率（每秒）： | 250k |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 1.25mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 1 个伪差分，单极 |
| 配用： | EVAL-AD7942CB-ND - BOARD EVALUATION FOR AD7942 |
AD7942
Rev. B | Page 21 of 2
4
Chain Mode Without Busy Indicator
This mode can be used to daisy-chain multiple AD7942s on
a 3-wire serial interface. This feature is useful for reducing
component count and wiring connections, for example, in
isolated multiconverter applications or for systems with a
limited interfacing capacity. Data readback is analogous to
clocking a shift register. A connection diagram example using
two AD7942s is shown in Figure 38 and the corresponding
timing diagram is given in Figure 39.
When SDI and CNV are low, SDO is driven low. With SCK
low, a rising edge on CNV initiates a conversion, selects the
chain mode, and disables the busy indicator. In this mode, CNV
is held high during the conversion phase and the subsequent
data readback. When the conversion is complete, the MSB is
output onto SDO and the AD7942 enters the acquisition phase
and powers down. The remaining data bits stored in the inter-
nal shift register are then clocked by subsequent SCK falling
edges. For each ADC, SDI feeds the input of the internal shift
register and is clocked by the SCK falling edge. Each ADC in
the chain outputs its data MSB first and 14 × N clocks are
required to readback the N ADCs. The data is valid on both
SCK edges. Although the rising edge can be used to capture
the data, a digital host also using the SCK falling edge allows
a faster reading rate and consequently more AD7942s in the
chain, provided the digital host has an acceptable hold time.
The maximum conversion rate may be reduced due to the total
readback time. For instance, with a 5 ns digital host setup time
and 3 V interface, up to eight AD7942s running at a conversion
rate of 220 kSPS can be daisy-chained on a 3-wire port.
CNV
SCK
SDO
SDI
CLK
CONVERT
DATA IN
DIGITAL HOST
AD7942
B
CNV
SCK
SDO
SDI AD7942
A
04
65
7-
0
38
Figure 38. Chain Mode Without Busy Indicator Connection Diagram
SDOA = SDIB
DA13
DA12
DA11
SCK
1
2
3
262728
tSSDISCK
tHSDISCK
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV
DA1
12
13
tSCK
tSCKL
tSCKH
DA0
15
16
14
SDIA = 0
SDOB
DB13
DB12
DB11
DA1
DB1DB0DA13
DA12
tHSDO
tDSDO
tSSCKCNV
tHSCKCNV
DA0
04
65
7-
0
39
Figure 39. Chain Mode Without Busy Indicator, Serial Interface Timing
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