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| 型号： | AD7982BRMZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 15/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC 18BIT 1MSPS PULSAR 10MSOP |
| 产品培训模块： | Motor Control |
| 设计资源： | Converting a Single-Ended Signal with AD7982 Differential PulSAR ADC (CN0032) Precision Single-Supply Differential ADC Driver for Industrial-Level Signals (CN0180) |
| 标准包装： | 1 |
| 系列： | PulSAR® |
| 位数： | 18 |
| 采样率（每秒）： | 1M |
| 数据接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 8.6mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 10-TFSOP，10-MSOP（0.118"，3.00mm 宽） |
| 供应商设备封装： | 10-MSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个差分，单极 |
| 产品目录页面： | 780 (CN2011-ZH PDF) |
AD7982
Data Sheet
Rev. B | Page 22 of 24
CHAIN MODE WITH BUSY INDICATOR
This mode can also be used to daisy-chain multiple AD7982s
on a 3-wire serial interface while providing a busy indicator.
This feature is useful for reducing component count and wiring
connections, for example, in isolated multiconverter applications or
for systems with a limited interfacing capacity. Data readback is
analogous to clocking a shift register.
A connection diagram example using three AD7982s is shown
in Figure 39, and the corresponding timing is given in Figure 40.
When SDI and CNV are low, SDO is driven low. With SCK
high, a rising edge on CNV initiates a conversion, selects the
chain mode, and enables the busy indicator feature. In this
mode, CNV is held high during the conversion phase and the
subsequent data readback. When all ADCs in the chain have
completed their conversions, the SDO pin of the ADC closest to
the digital host (see the AD7982 ADC labeled C in Figure 39) is
driven high. This transition on SDO can be used as a busy indicator
to trigger the data readback controlled by the digital host. The
AD7982 then enters the acquisition phase and powers down.
The data bits stored in the internal shift register are clocked out,
MSB first, by subsequent SCK falling edges. For each ADC, SDI
feeds the input of the internal shift register and is clocked by the
SCK falling edge. Each ADC in the chain outputs its data MSB
first, and 18 × N + 1 clocks are required to read back the N ADCs.
Although the rising edge can be used to capture the data, a digital
host using the SCK falling edge allows a faster reading rate and
consequently more AD7982s in the chain, provided the digital
host has an acceptable hold time.
CONVERT
DATA IN
CLK
DIGITAL HOST
06513-
026
AD7982
SDI
SDO
CNV
C
SCK
AD7982
SDI
SDO
CNV
A
SCK
IRQ
AD7982
SDI
SDO
CNV
B
SCK
Figure 39. Chain Mode with Busy Indicator Connection Diagram
SDOA = SDIB
DA17 DA16 DA15
SCK
1
2
3
39
53
54
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
CNV = SDIA
DA1
4
17
tSCK
tSCKH
tSCKL
DA0
19
38
18
SDOB = SDIC
DB17 DB16 DB15
DA1
DB1
DB0 DA17 DA16
55
tSSDISCK
tHSDISCK
tHSDO
tDSDO
SDOC
DC17 DC16 DC15
DA1
DA0
DC1
DC0
DA16
21
35
36
20
37
DB1
DB0 DA17
DB17 DB16
tDSDOSDI
tSSCKCNV
tHSCKCNV
DA0
tDSDOSDI
06513-
027
Figure 40. Chain Mode with Busy Indicator Serial Interface Timing
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