参数资料
型号: AD7982BRMZ
厂商: Analog Devices Inc
文件页数: 8/24页
文件大小: 0K
描述: IC ADC 18BIT 1MSPS PULSAR 10MSOP
产品培训模块: Motor Control
设计资源: Converting a Single-Ended Signal with AD7982 Differential PulSAR ADC (CN0032)
Precision Single-Supply Differential ADC Driver for Industrial-Level Signals (CN0180)
标准包装: 1
系列: PulSAR®
位数: 18
采样率(每秒): 1M
数据接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
转换器数目: 1
功率耗散(最大): 8.6mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 10-TFSOP,10-MSOP(0.118",3.00mm 宽)
供应商设备封装: 10-MSOP
包装: 管件
输入数目和类型: 1 个差分,单极
产品目录页面: 780 (CN2011-ZH PDF)
AD7982
Data Sheet
Rev. B | Page 16 of 24
DIGITAL INTERFACE
Although the AD7982 has a reduced number of pins, it offers
flexibility in its serial interface modes.
When in CS mode, the AD7982 is compatible with SPI, QSPI,
digital hosts, and DSPs. In this mode, the AD7982 can use
either a 3-wire or 4-wire interface. A 3-wire interface using the
CNV, SCK, and SDO signals minimizes wiring connections
useful, for instance, in isolated applications. A 4-wire interface
using the SDI, CNV, SCK, and SDO signals allows CNV, which
initiates the conversions, to be independent of the readback
timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
When in chain mode, the AD7982 provides a daisy-chain feature
using the SDI input for cascading multiple ADCs on a single
data line similar to a shift register.
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. The CS mode is selected if
SDI is high, and the chain mode is selected if SDI is low. The
SDI hold time is such that when SDI and CNV are connected
together, the chain mode is always selected.
In either mode, the AD7982 offers the option of forcing a start
bit in front of the data bits. This start bit can be used as a busy
signal indicator to interrupt the digital host and trigger the data
reading. Otherwise, without a busy indicator, the user must timeout
the maximum conversion time prior to readback.
The busy indicator feature is enabled
In the CS mode if CNV or SDI is low when the ADC
conversion ends (see Figure 32 and Figure 36).
In the chain mode if SCK is high during the CNV rising
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