参数资料
| 型号： | AD8011ANZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/17页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP CF LP LDIST 30MA 8DIP |
| 标准包装： | 50 |
| 放大器类型： | 电流反馈 |
| 电路数： | 1 |
| 转换速率： | 3500 V/µs |
| -3db带宽： | 400MHz |
| 电流 - 输入偏压： | 5µA |
| 电压 - 输入偏移： | 2000µV |
| 电流 - 电源： | 1.3mA |
| 电流 - 输出 / 通道： | 30mA |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 12 V，±1.5 V ~ 6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
| 产品目录页面： | 769 (CN2011-ZH PDF) |
REV. C
–12–
AD8011
40
30
20
010
15
20
25
CL (pF)
10
R
SERIES
(
)
5
Figure 12. Recommended RSERIES vs. Capacitive
Load for
≤ 30 ns Settling to 0.1%
OPTIMIZING FLATNESS
As mentioned, the previous ac transfer equations are based on a
simplified single-pole model. Due to the device’s internal para-
sitics (primarily CP1/CP1B and CP2 in Figure 6) and external
package/board parasites (partially represented in Figure 12) the
computed BW, using the previous VO (s) equation, typically will
be lower than the AD8011’s measured small signal BW. See
data sheet Bode plots.
With only internal parasitics included, the BW is extended due
to the complex pole pairs created primarily by CP1/CP2B and
CP2 versus the single-pole assumption shown above. This
results in a design controlled, closed-loop damping factor ( ) of
nominally 0.6 resulting in the CLBW increasing by approxi-
mately 1.3
higher than the computed single-pole value above
for optimized external gains of +2/–1. As external noninverting
gain (G) is increased, the actual closed-loop bandwidth versus
the computed single-pole ac response is in closer agreement.
Inverting pin and external component capacitance (designated CP)
will further extend the CLBW due to the closed-loop zero created
by CP and RN RF when operating in the noninverting mode. Using
proper RF component and layout techniques (see the Layout
Considerations section), this capacitance should be about 1.5 pF.
This results in a further incremental BW increase of almost 2
(versus the computed value) for G = +1 decreasing and approach-
ing its complex pole pair BW for gains approaching +6 or higher.
As previously discussed, the single-pole response begins to corre-
late well. Note that a pole is also created by 1/2 gmf and CP, which
prevents the AD8011 from becoming unstable. This parasitic
has the greatest effect on BW and peaking for low positive gains
as the data sheet Bode plots clearly show. For inverting operation,
CP has relatively much less effect on CLBW variation.
11
10
9
8
7
5
4
3
6
2
1
10
100
500
FREQUENCY (MHz)
GAIN
(dB)
RF = 1k
RF = 750
VS = 5V
G = +2
VIN = 200mV
Figure 13. Flatness vs. Feedback
Output pin and external component capacitance (designated CL)
will further extend the devices BW and can also cause peaking
below and above the CLBW if too high. In the time domain,
poor step settling characteristics (ringing up to about 2 GHz
and excessive overshoot) can result. For high CL values greater
than about 5 pF, an external series damping resistor is recom-
mended. For light loads, any output capacitance will reflect on
A2’s output (Z2 of buffer A3) as both added capacitance near
the CLBW (CLBW > fT/B) and eventually negative resistance at
much higher frequencies. These added effects are proportional
to the load C. This reflected capacitance and negative resistance
has the effect of both reducing A2’s phase margin and causing
high frequency, L
C, peaking respectively. Using an external
series resistor (as previously specified) reduces these unwanted
effects by creating a reflected zero to A2’s output, which will
reduce the peaking and eliminate ringing. For heavy resistive
loads, relatively more load C would be required to cause these
same effects.
High inductive parasitics, especially on the supplies and inverting/
noninverting inputs, can cause modulated low level RF ringing on
the output in the transient domain. Proper RF component and
board layout practices need to be observed. Relatively high para-
sitic lead inductance (roughly L >15 nh) can result in L
C
underdamped ringing. Here L/C means all associated input pins,
external components, and lead frame strays, including collector
to substrate device capacitance. In the ac domain, this L
C
resonance effect would typically not appear in the pass band of
the amplifier but would appear in the open-loop response at
frequencies well above the CLBW of the amplifier.
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相关代理商/技术参数 |
参数描述 |
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| AD8011AR | 功能描述:IC OPAMP CF LP LDIST 30MA 8SOIC RoHS:否 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:50 系列:- 放大器类型:J-FET 电路数:2 输出类型:- 转换速率:13 V/µs 增益带宽积:3MHz -3db带宽:- 电流 - 输入偏压:65pA 电压 - 输入偏移:3000µV 电流 - 电源:1.4mA 电流 - 输出 / 通道:- 电压 - 电源，单路/双路(±):7 V ~ 36 V，±3.5 V ~ 18 V 工作温度:-40°C ~ 85°C 安装类型:通孔 封装/外壳:8-DIP（0.300"，7.62mm） 供应商设备封装:8-PDIP 包装:管件 |
| AD8011AR-EBZ | 功能描述:BOARD EVAL FOR AD8011AR RoHS:是 类别:编程器，开发系统 >> 评估板 - 运算放大器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- |
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| AD8011AR-REEL7 | 功能描述:IC OPAMP CF LP LDIST 30MA 8SOIC RoHS:否 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:2,500 系列:- 放大器类型:通用 电路数:1 输出类型:满摆幅 转换速率:0.11 V/µs 增益带宽积:350kHz -3db带宽:- 电流 - 输入偏压:4nA 电压 - 输入偏移:20µV 电流 - 电源:260µA 电流 - 输出 / 通道:20mA 电压 - 电源，单路/双路(±):2.7 V ~ 36 V，±1.35 V ~ 18 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SO 包装:带卷 (TR) |
| AD8011ARZ | 功能描述:IC OPAMP CF LP LDIST 30MA 8SOIC RoHS:是 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:2,500 系列:- 放大器类型:通用 电路数:4 输出类型:- 转换速率:0.6 V/µs 增益带宽积:1MHz -3db带宽:- 电流 - 输入偏压:45nA 电压 - 输入偏移:2000µV 电流 - 电源:1.4mA 电流 - 输出 / 通道:40mA 电压 - 电源，单路/双路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:14-TSSOP 包装:带卷 (TR) 其它名称:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
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