参数资料
| 型号： | AD8151ASTZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/40页 |
| 文件大小： | 0K |
| 描述： | IC CROSSPOINT SWIT 33X17 184LQFP |
| 标准包装： | 1 |
| 系列： | XStream™ |
| 功能： | 交叉点开关 |
| 电路： | 1 x 33:17 |
| 电压电源： | 双电源 |
| 电压 - 电源，单路/双路(±)： | ±3 V ~ 5.25 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 184-LQFP |
| 供应商设备封装： | 184-LQFP（20x20） |
| 包装： | 托盘 |
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AD8151
Rev. B | Page 18 of 40
RE Input
Second Rank Read-Enable. Forcing this pin to logic low enables
the output drivers on the bidirectional D pins [6:0], entering
the readback mode of operation. By selecting an output address
with the A pins [4:0] and forcing RE to logic low, the 7-bit
data stored in the second rank latch for that output address is
written to the D pins [6:0]. Data should not be written to the
D pins [6:0] externally while in readback mode.
The RE and WE pins are not exclusive, and can be used at the
same time, but data should not be written to the D pins [6:0]
from external sources while in readback mode.
CS Input
Chip-Select. This pin must be forced to logic low to program or
receive data from the logic interface, with the exception of the
RESET pin, described in the next section. This pin has no
effect on the signal pairs and does not alter any of the stored
control data.
RESET Input
Global Output Disable Pin. Forcing the RESET pin to logic low
resets the enable bit, D6, in all 17 second rank latches,
regardless of the state of any of the other pins. This has the
effect of immediately disabling the 17 output signal pairs in the
matrix.
It is useful to momentarily hold RESET at a logic low state when
powering up the AD8151 in a system that has multiple output
signal pairs connected together. Failure to do this can result in
several signal outputs contending after power-up. The RESET
pin is not gated by the state of the chip-select pin, CS. It should
be noted that the RESET pin does not program the first rank,
which contains undefined data after power-up.
CONTROL INTERFACE TRANSLATORS
The AD8151 control interface has two supply pins, VDD and VSS.
The potential between the positive logic supply, VDD, and the
negative logic supply, VSS, must be at least 3 V and no more than
5 V. Regardless of supply, the logic threshold is approximately
1.6 V above VSS, allowing the interface to be used with most
CMOS and TTL logic drivers. The signal matrix supplies, VCC
and VEE, can be set independently of the voltage on VDD and VSS,
with the constraints that (VDD VEE) ≤ 10 V. These constraints
allow operation of the control interface on 3 V or 5 V, while the
signal matrix is operated on 3.3 V or 5 V PECL or –3.3 V or
–5 V ECL.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD8151-EVAL | 制造商:Analog Devices 功能描述:EVAL KIT FOR 33 17, 3.2 GBPS DGTL CROSSPOINT SWIT - Bulk |
| AD8151XSTZ | 功能描述:IC CROSSPOINT SWITCH 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD8152 | 制造商:AD 制造商全称:Analog Devices 功能描述:34 x 34, 3.2 Gbps Asynchronous Digital Crosspoint Switch |
| AD8152-EVAL | 制造商:Analog Devices 功能描述:EVAL KIT FOR ASYNCH DGTL CROSSPOINT SWIT - Bulk |
| AD8152JBP | 功能描述:IC CROSSPOINT SWIT 34X34 256BGA RoHS:否 类别:集成电路 (IC) >> 接口 - 模拟开关，多路复用器，多路分解器 系列:XStream™ 其它有关文件:STG4159 View All Specifications 标准包装:5,000 系列:- 功能:开关 电路:1 x SPDT 导通状态电阻:300 毫欧 电压电源:双电源 电压 - 电源，单路/双路(±):±1.65 V ~ 4.8 V 电流 - 电源:50nA 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:7-WFBGA，FCBGA 供应商设备封装:7-覆晶 包装:带卷 (TR) |
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