参数资料
型号: AD8151ASTZ
厂商: Analog Devices Inc
文件页数: 17/40页
文件大小: 0K
描述: IC CROSSPOINT SWIT 33X17 184LQFP
标准包装: 1
系列: XStream™
功能: 交叉点开关
电路: 1 x 33:17
电压电源: 双电源
电压 - 电源,单路/双路(±): ±3 V ~ 5.25 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 184-LQFP
供应商设备封装: 184-LQFP(20x20)
包装: 托盘
AD8151
Rev. B | Page 24 of 40
POWER SUPPLIES
The AD8151 is designed to work with standard ECL logic
levels. This means that VCC is at ground and VEE is at a negative
supply. The shells of the I/O SMA connectors are at VCC
potential. Thus, when operating in the standard ECL
configuration, test equipment can be directly connected to the
board, since the test equipment also has its connector shells at
ground potential.
Operating in PECL mode requires VCC to be at a positive
voltage while VEE is at ground. Since this generates a positive
voltage at the shells of the I/O connectors, it can cause problems
when directly connecting to test equipment. Some equipment,
such as battery-operated oscilloscopes, can be floated from
ground, but care should be taken with line-powered equipment
to avoid creating a dangerous situation. Refer to the manual of
the test equipment that is being used.
The voltage difference from VCC to VEE can range from 3 V to
5 V. Power savings can be realized by operating at a lower
voltage without any compromise in performance.
A separate connection is provided for VTT, the termination
potential of the outputs. This can be at a voltage as high as VCC,
but power savings can be realized if VTT is at a voltage that is
somewhat lower.
As a practical matter, current on the evaluation board flows
from the VTT supply through the termination resistors into the
multiple outputs of the AD8151 and to the VEE supply. When
running in ECL mode, VTT should be at a negative supply.
Most power supplies do not allow a simultaneous ground
connection to VCC and a negative supply at VTT, because it
would force the source current to originate from a negative
supply, which wants to flow to the more-negative VEE. In this
case, the source current does not then return to the ground
terminal of the VTT supply. Thus, VTT should be referenced to
VEE when running in ECL mode or a true bipolar supply should
be used.
The digital supply is provided to the AD8151 by the VDD and
VSS pins. VSS should always be at ground potential to make it
compatible with standard CMOS or TTL logic. VDD can range
from 3 V to 5 V, and should be matched to the supply voltage of
the logic used to control the AD8151. However, since PCs use
5 V logic on their parallel port, VDD should be 5 V when using a
PC to program the AD8151.
Bypassing
Most of the board’s bypass capacitors are opposite the DUT on
the solder side and are connected between VCC and VEE. This is
where they are most effective. For low inductance, use 0.01 μF
ceramic chip capacitors.
There are additional higher value capacitors elsewhere on the
board for bypassing at lower frequencies. The location of these
capacitors is not as critical.
Input and Output Considerations
Each input contains a 100 Ω differential termination. Although
differential termination eases board layout due to its compact
nature, it can cause problems with the driving generator. A typical
pulse or pattern generator wants to see 50 Ω to ground (or to –2 V
in some cases). High speed probing of the input has shown that if
this type of termination is not present, input amplitudes can be
slightly off. The dc input levels can be even more affected.
Depending on the generator used, these levels can be off as much as
800 mV in either direction. A correction for this problem is to
attach a 6 dB attenuator to each P and N input. Because the
AD8151 has a large common-mode voltage range on its input
stage, it is not significantly affected by dc level errors.
On this evaluation board, all unused inputs are tied to VCC
(GND). All outputs, whether attached to connectors or not, are
tied to VTT through a 49.9 Ω resistor. The AD8151 device is on
the component side of the board, while input terminations and
output back terminations are on the circuit side. The input
signals from the circuit side transit through via holes to the
DUT’s pads. The component-side output signals connect to via
holes and to circuit-side 49.9 Ω termination resistors.
Board Construction
For this board, FR4 material was chosen over more exotic board
materials. Tests show exotic materials are unnecessary. This is a
4-layer board, so power is bused on both external and internal
layers. Test structures show microstrip performance is unaf-
fected by the dc bias levels on the plane beneath it.
The board manufacturing process should ensure a controlled
impedance board. The board stack consists of a 5-mil-thick
layer between external and internal layers. This allows the use of
an 8-mil-wide microstrip trace running from the SMA con-
nector to the DUT’s pads. The narrow trace eliminates the need
to reduce the trace width as the DUT’s pads are approached and
helps to control the microstrip trace impedance. The thin 5-mil
dielectric also reduces crosstalk by confining the electromag-
netic fields between the trace and the plane below.
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