
AD8191A
Rev. 0 | Page 18 of 28
SERIAL INTERFACE CONFIGURATION REGISTERS
The serial interface configuration registers can be read and written using the I2C serial control interface, Pin I2C_SDA, and Pin I2C_SCL.
The least significant bits of the AD8191A I2C part address are set by tying Pin I2C_ADDR2, Pin I2C_ADDR1, and Pin I2C_ADDR0 to
3.3 V (Logic 1) or 0 V (Logic 0). As soon as the serial control interface is used, the parallel control interface is disabled until the AD8191A
Table 5. Serial (I2C) Interface Register Map
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Addr
Default
High
speed
switch
enable
High speed source select
High Speed
Device
Modes
HS_EN
0
HS_CH[1]
HS_CH[0]
0x00
0x40
Auxiliary
switch
enable
Auxiliary switch source select
Auxiliary
Device
Modes
AUX_EN
0
AUX_CH[1]
AUX_CH[0]
0x01
0x40
High speed
input
termination
select
Receiver
Settings
RX_TO
0x10
0x01
Source A and Source B: input termination pulse-on-source switch select
(disconnect termination for a short period of time)
Input
Termination
Pulse
Register 1
RX_PT[7]
RX_PT[6]
RX_PT[5]
RX_PT[4]
RX_PT[3]
RX_PT[2]
RX_PT[1]
RX_PT[0]
0x11
0x00
Source C and Source D: input termination pulse-on-source switch select
(disconnect termination for a short period of time)
Input
Termination
Pulse
Register 2
RX_PT[15]
RX_PO[14]
RX_PT[13]
RX_PT[12]
RX_PT[11]
RX_PT[10]
RX_PT[9]
RX_PT[8]
0x12
0x00
Source A and Source B: input equalization level select
Receive
Equalizer
Register 1
RX_EQ[7]
RX_EQ[6]
RX_EQ[5]
RX_EQ[4]
RX_EQ[3]
RX_EQ[2]
RX_EQ[1]
RX_EQ[0]
0x13
0x00
Source C and Source D: input equalization level select
Receive
Equalizer
Register 2
RX_EQ[15]
RX_EQ[14]
RX_EQ[13]
RX_EQ[12]
RX_EQ[11]
RX_EQ[10]
RX_EQ[9]
RX_EQ[8]
0x14
0x00
High speed output
pre-emphasis level select
High speed
output
termination
select
High speed
output current
level select
Transmitter
Settings
TX_PE[1]
TX_PE[0]
TX_PTO
TX_OCL
0x20
0x03
HIGH SPEED DEVICE MODES REGISTER
HS_EN: High Speed (TMDS) Channels Enable Bit
Table 6. HS_EN Description
HS_EN
Description
0
High speed channels off, low power/standby mode
1
High speed channels on
HS_CH[1:0]: High Speed (TMDS) Switch Source Select Bus
Table 7. HS_CH Mapping
HS_CH[1:0]
O[3:0]
Description
00
A[3:0]
High Speed Source A switched to output
01
B[3:0]
High Speed Source B switched to output
10
C[3:0]
High Speed Source C switched to output
11
D[3:0]
High Speed Source D switched to output
AUXILIARY DEVICE MODES REGISTER
AUX_EN: Auxiliary (Low Speed) Switch Enable Bit
Table 8. AUX_EN Description
AUX_EN
Description
0
Auxiliary switch off, no low speed input/output to
low speed common input/output connection
1
Auxiliary switch on