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| 型号： | AD824AR-14-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC OPAMP JFET R-R 2MHZ LP 14SOIC |
| 标准包装： | 2,500 |
| 放大器类型： | J-FET |
| 电路数： | 4 |
| 输出类型： | 满摆幅 |
| 转换速率： | 2 V/µs |
| 增益带宽积： | 2MHz |
| -3db带宽： | 2MHz |
| 电流 - 输入偏压： | 4pA |
| 电压 - 输入偏移： | 500µV |
| 电流 - 电源： | 560µA |
| 电流 - 输出 / 通道： | 12mA |
| 电压 - 电源，单路/双路(±)： | 3 V ~ 30 V，±1.5 V ~ 15 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SOIC |
| 包装： | 带卷 (TR) |
REV. C
AD824
–14–
A design consideration in sample-and-hold circuits is voltage
droop at the output caused by op amp bias and switch leakage
currents. By choosing a JFET op amp and a low leakage CMOS
switch, this design minimizes droop rate error to better than
0.1
mV/ms in this circuit. Higher values of CH will yield a lower
droop rate. For best performance, CH and C2 should be poly-
styrene, polypropylene or Teflon capacitors. These types of
capacitors exhibit low leakage and low dielectric absorption. Addi-
tionally, 1% metal film resistors were used throughout the design.
In the sample mode, SW1 and SW4 are closed, and the output
is VOUT = –VIN. The purpose of SW4, which operates in parallel
with SW1, is to reduce the pedestal, or hold step, error by
injecting the same amount of charge into the noninverting input
of A3 that SW1 injects into the inverting input of A3. This
creates a common-mode voltage across the inputs of A3 and is
then rejected by the CMR of A3; otherwise, the charge injection
from SW1 would create a differential voltage step error that
would appear at VOUT. The pedestal error for this circuit is
less than 2 mV over the entire 0 V to 3.3 V/5 V signal range.
Another method of reducing pedestal error is to reduce the pulse
amplitude applied to the control pins. In order to control the
ADG513, only 2.4 V are required for the “ON” state and
0.8V for the “OFF” state. If possible, use an input control
signal whose amplitude ranges from 0.8 V to 2.4 V instead of a
full range 0 V to 3.3 V/5 V for minimum pedestal error.
Other circuit features include an acquisition time of less than
3
ms to 1%; reducing CH and C2 will speed up the acquisition
time further, but an increased pedestal error will result. Settling
time is less than 300 ns to 1%, and the sample-mode signal BW
is 80 kHz.
The ADG513 was chosen for its ability to work with 3 V/5 V
supplies and for having normallyopen and normallyclosed preci-
sion CMOS switches on a dielectrically isolated process. SW2 is
not required in this circuit; however, it was used in parallel with
SW3 to provide a lower RON analog switch.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD824AR-14-REEL7 | 功能描述:IC OPAMP JFET R-R 2MHZ LP 14SOIC RoHS:否 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:150 系列:- 放大器类型:音频 电路数:2 输出类型:- 转换速率:5 V/µs 增益带宽积:12MHz -3db带宽:- 电流 - 输入偏压:100nA 电压 - 输入偏移:500µV 电流 - 电源:6mA 电流 - 输出 / 通道:50mA 电压 - 电源，单路/双路(±):4 V ~ 32 V，±2 V ~ 16 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:8-TSSOP 包装:管件 |
| AD824AR-16 | 制造商:Analog Devices 功能描述: 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:QUAD OP-AMP, 4000 uV OFFSET-MAX, 2 MHz BAND WIDTH, PDSO16 |
| AD824AR-16-REEL | 制造商:Analog Devices 功能描述:OP Amp Quad GP R-R O/P ±15V/30V 16-Pin SOIC N T/R |
| AD824AR-3V | 制造商:AD 制造商全称:Analog Devices 功能描述:Single Supply, Rail-to-Rail Low Power, FET-Input Op Amp |
| AD824ARZ-14 | 功能描述:IC OPAMP JFET R-R 2MHZ LP 14SOIC RoHS:是 类别:集成电路 (IC) >> Linear - Amplifiers - Instrumentation 系列:- 标准包装:2,500 系列:- 放大器类型:通用 电路数:4 输出类型:- 转换速率:0.6 V/µs 增益带宽积:1MHz -3db带宽:- 电流 - 输入偏压:45nA 电压 - 输入偏移:2000µV 电流 - 电源:1.4mA 电流 - 输出 / 通道:40mA 电压 - 电源，单路/双路(±):3 V ~ 32 V，±1.5 V ~ 16 V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:14-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:14-TSSOP 包装:带卷 (TR) 其它名称:LM324ADTBR2G-NDLM324ADTBR2GOSTR |
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