参数资料
| 型号： | AD8306AR |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC LOGARITHM AMP 5-400MHZ 16SOIC |
| 标准包装： | 1 |
| 类型： | 限制-对数放大器 |
| 应用： | 接收器信号强度指示（RSSI） |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 16-SO |
| 包装： | 管件 |
REV. A
AD8306
–11–
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
0.1 F
R2
10
NC
RLIM
RSSI
0.1 F
R1
10
ENABLE
RT
52.3
C1
0.01 F
SIGNAL
INPUTS
NC = NO CONNECT
12
13
VS (2.7V TO 6.5V)
C2
0.01 F
(SEE TEXT)
0.01 F
LIMITER
OUTPUT
RLOAD
RL
Figure 27. Basic Connections for Operating the Limiter
Depending on the application, the resulting voltage may be used
in a fully balanced or unbalanced manner. It is good practice to
retain both load resistors, even when only one output pin is
used. These should always be returned to the same well de-
coupled node on the PC board (see layout of evaluation board).
The unbalanced, or single-sided mode, is more inclined to result
in instabilities caused by the very high gain of the signal path.
The limiter current may be set as high as 10 mA (which requires
RLIM to be 40 ) and can be optionally increased somewhat
beyond this level. It is generally inadvisable, however, to use a
high bias current, since the gain of this wide bandwidth signal
path is proportional to the bias current, and the risk of instabil-
ity is elevated as RLIM is reduced (recommended value is 400 ).
However, as the size of RLOAD is increased, the bandwidth of the
limiter output decreases from 585 MHz for RLOAD = RLIM =
50
to 50 MHz for R
LOAD = RLIM = 400 (bandwidth =
210 MHz for RLOAD = RLIM = 100 and 100 MHz for RLOAD =
RLIM = 200 ). As a result, the minimum necessary limiter
output level should be chosen while maintaining the required
limiter bandwidth. For RLIM = RLOAD = 50 , the limiter output
is specified for input levels between –78 dBV (–65 dBm) and
+9 dBV (+22 dBm). The output of the limiter may be unstable
for levels below –78 dBV (–65 dBm). However, keeping RLIM
above 100
will make instabilities on the output less likely for
input levels below –78 dBV.
A transformer or a balun (e.g., MACOM part number ETC1-1-13)
can be used to convert the differential limiter output voltages to
a single-ended signal.
Input Matching
Where either a higher sensitivity or a better high frequency
match is required, an input matching network is valuable. Using
a flux-coupled transformer to achieve the impedance transfor-
mation also eliminates the need for coupling capacitors, lowers
any dc offset voltages generated directly at the input, and use-
fully balances the drives to INHI and INLO, permitting full
utilization of the unusually large input voltage capacity of the
AD8306.
The choice of turns ratio will depend somewhat on the fre-
quency. At frequencies below 30 MHz, the reactance of the
input capacitance is much higher than the real part of the input
impedance. In this frequency range, a turns ratio of 2:9 will
lower the effective input impedance to 50
while raising the
input voltage by 13 dB. However, this does not lower the effect
of the short circuit noise voltage by the same factor, since there
will be a contribution from the input noise current. Thus, the
total noise will be reduced by a smaller factor. The intercept at
the primary input will be lowered to –121 dBV (–108 dBm).
Impedance matching and drive balancing using a flux-coupled
transformer is useful whenever broadband coupling is required.
However, this may not always be convenient. At high frequen-
cies, it will often be preferable to use a narrow-band matching
network, as shown in Figure 28, which has several advantages.
First, the same voltage gain can be achieved, providing increased
sensitivity, but now a measure of selectively is simultaneously
introduced. Second, the component count is low: two capacitors
and an inexpensive chip inductor are needed. Third, the net-
work also serves as a balun. Analysis of this network shows that
the amplitude of the voltages at INHI and INLO are quite simi-
lar when the impedance ratio is fairly high (i.e., 50
to 1000 ).
1
2
3
4
5
6
7
8
VLOG
VPS2
PADL
LMHI
LMLO
PADL
FLTR
LMDR
COM2
VPS1
PADL
INHI
INLO
PADL
COM1
ENBL
AD8306
9
10
11
14
15
16
0.1 F
10
NC
RLIM
RSSI
LIMITER
OUTPUT
0.1 F
10
C2 = CM
ZIN
NC = NO CONNECT
12
13
VS
C1 = CM
LM
Figure 28. High Frequency Input Matching Network
Figure 29 shows the response for a center frequency of 100 MHz.
The response is down by 50 dB at one-tenth the center frequency,
falling by 40 dB per decade below this. The very high frequency
attenuation is relatively small, however, since in the limiting
case it is determined simply by the ratio of the AD8306’s input
capacitance to the coupling capacitors. Table I provides solu-
tions for a variety of center frequencies fC and matching from
impedances ZIN of nominally 50 and 100 . Exact values are
shown, and some judgment is needed in utilizing the nearest
standard values.
FREQUENCY – MHz
14
60
DECIBELS
13
12
11
10
9
8
7
6
5
70
80
90
100
110
120
130
4
3
2
1
0
–1
140
150
GAIN
INPUT AT
TERMINATION
Figure 29. Response of 100 MHz Matching Network
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