参数资料
型号: AD8347ARUZ-REEL7
厂商: ANALOG DEVICES INC
元件分类: 调制器/解调器
英文描述: 800 MHz - 2700 MHz RF/MICROWAVE QUADRAPHASE DEMODULATOR
封装: MO-153AE, RU-28, TSSOP-28
文件页数: 11/28页
文件大小: 623K
代理商: AD8347ARUZ-REEL7
AD8347
Rev. A | Page 19 of 28
LOIN
LOIP
AD8347
100pF
200
Ω
LO
02675-047
Figure 47. Single-Ended LO Drive
OPERATING THE VGA
A three-stage VGA sets the gain in the RF section. Two of the
three stages come before the mixer while the third amplifies the
mixer output. All three stages are driven in parallel. The gain
range of the first RF VGA and that of the second RF VGA
combined with the mixer are both 13 dB to +10 dB. The gain
range of the baseband VGA is 4 dB to +19.5 dB. Therefore, the
overall gain range from the RF input to the IMXO and QMXO
pins is 30 dB to approximately +39.5 dB.
The gain of the VGA is set by the voltage on the VGIN pin,
which is a high impedance input. The gain control function
(which is linear-in-dB) and linearity are shown in Figure 4 and
Figure 5 at 1.9 GHz. Note that the sense of the gain control
voltage is negative because as the gain control voltage ranges
from 0.2 V to 1.2 V, the gain decreases from +39.5 dB to 30 dB.
MIXER OUTPUT LEVEL AND DRIVE CAPABILITY
I- and Q-channel baseband outputs, IMXO and QMXO, are
low impedance outputs (ROUT @ 3 Ω) with bias levels equal to
VVREF, the voltage on Pin 14. The achievable output levels on
IMXO/QMXO are limited by their current drive capability of
1.5 mA maximum. This allows for a 600 mV p-p swing into a
200 Ω load. At lower output levels, IMXO and QMXO can drive
smaller load resistances, subject to the same current limit.
These output stages are not, however, designed to directly drive
50 Ω loads.
OPERATING THE VGA IN AGC MODE
Although the VGA can be driven by an external source such as
a DAC, the AD8347 has an on-board sum of squares detector to
allow the AD8347 to operate in an automatic leveling mode.
Due to the nature of the detector, an input signal with a higher
peak-to-average ratio causes the AGC loop to settle with a
higher mixer output peak-to-peak voltage. In this data sheet,
peak-to-peak calculations assume a sine wave input when
referencing AGC operation.
The connections for operating in this mode are shown in
Figure 46. The two mixer outputs are connected to Detector
Input VDT1 and Detector Input VDT2. The summed detector
output drives an internal integrator which, in turn, delivers a
gain correction voltage to the VAGC pin. A 0.1 μF capacitor
from VAGC to ground sets the dominant pole of the integrator
circuit. VAGC, which should be connected to VGIN, adjusts
gain until an internal threshold is reached. This threshold
corresponds to a level at the IMXO and QMXO pins of approxi-
mately 8.5 mV rms. This level changes slightly as a function of
RF input power (see Figure 34). For a CW (sine wave) input,
this corresponds to approximately 24 mV p-p. If this signal is
applied directly to the subsequent baseband amplifier stage,
the final baseband output is 760 mV p-p differential. See the
If the VGA gain is set from an external source, VDT1 and
VDT2 (the on-board detector inputs) are not used and are tied
to VREF.
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