参数资料
型号: AD834JRZ-RL
厂商: Analog Devices Inc
文件页数: 8/20页
文件大小: 0K
描述: IC MULTIPLIER 4-QUADRANT 8-SOIC
标准包装: 2,500
功能: 模拟乘法器
位元/级数: 四象限
封装/外壳: 8-SOIC(0.154",3.90mm 宽)
供应商设备封装: 8-SO
包装: 带卷 (TR)
AD834
Data Sheet
Rev. F | Page 16 of 20
FREQUENCY DOUBLER
Figure 21 shows another squaring application. In this case, the
output filter has been removed and the wideband differential
output is converted to a single-sided signal using a balun, which
consists of a length of 50 Ω coaxial cable fed through a ferrite
core (Fair-Rite Type 2677006301). No attempt is made to reverse
terminate the output. Higher load power can be achieved by
replacing the 50 Ω load resistors with ferrite bead inductors.
The same precautions should be observed with regard to printed
circuit board (PCB) layout as recommended in the Power
spectrum shown in Figure 22 is for an input power of +10 dBm
at a frequency of 200 MHz. The second harmonic component at
400 MHz has an output power of 15 dBm. Some feedthrough
of the fundamental occurs; it is 15 dB below the main output. A
spurious output at 600 MHz is also present, but it is 30 dB
below the main output. At an input frequency of 100 MHz,
the measured power level at 200 MHz is 16 dBm, while the
fundamental feedthrough is reduced to 25 dB below the main
output; at an output of 600 MHz the power is 11 dBm and the
third harmonic at 900 MHz is 32 dB below the main output.
00894-
017
SMA FROM
HP8656A
GENERATOR
SMA TO
HP8656A
SPECTRUM
ANALYZER
8
7
6
5
1
2
3
4
X2
X1 +VS W1
Y1
Y2
–VS W2
AD834
0.1F
75
560pF
BALUN
+5V
10
49.9
–5V
25 125
125
25
Figure 21. Frequency Doubler Connections
00894-
018
FREQUENCY (MHz)
O
UT
P
UT
P
O
W
E
R
(
d
Bm)
–10
150
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
200
250
300
350
400
450
500
550
600
650
Figure 22. Output Spectrum for Configuration of Figure 21
WIDEBAND THREE-SIGNAL MULTIPLIER/DIVIDER
Two AD834 devices and a wideband op amp can be connected
to make a versatile multiplier/divider having the transfer
function
(
)(
)
(
)
Z
U2
U1
Y2
Y1
X2
X1
W
+
=
with a denominator range of about 100:1. The denominator
input U = U1 U2 must be positive and in the range 100 mV
to 10 V; X, Y, and Z inputs may have either polarity. Figure 23
shows a general configuration that may be simplified to suit a
particular application. This circuit accepts full-scale input voltages
of 10 V, and delivers a full-scale output voltage of 10 V. The optional
offset trim at the output of the AD834 improves the accuracy for
small denominator values. It is adjusted by nulling the output
voltage when the X and Y inputs are zero and U = 100 mV.
The op amp is internally compensated to be stable without the
use of any additional HF compensation. As Input U is reduced,
the bandwidth falls because the feedback around the op amp is
proportional to Input U. Note that, this circuit was originally
characterized using the AD840 op amp; some alternative op
amps include the AD818 and the AD8021.
This circuit can be modified in several ways. For example, if the
differential input feature is not needed, the unused input can be
connected to ground through a single resistor, equal to the parallel
sum of the resistors in the attenuator section. The full-scale input
levels on X, Y, and U can be adapted to any full-scale voltage
down to ±1 V by altering the attenuator ratios. Note, however,
that precautions must be taken if the attenuator ratio from the
output of A3 back to the second AD834 (A2) is lowered. First,
the HF compensation limit of the op amp may be exceeded if
the negative feedback factor is too high. Second, if the attenuated
output at the AD834 exceeds its clipping level of ±1.3 V, feedback
control is lost and the output suddenly jumps to the supply rails.
However, with these limitations understood, it is possible to adapt
the circuit to smaller full-scale inputs and/or outputs, for use
with lower supply voltages.
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