参数资料
型号: AD8383ACPZ
厂商: Analog Devices Inc
文件页数: 11/16页
文件大小: 0K
描述: IC DECIMATING LCD DRIVER 48LFCSP
产品变化通告: AD8383ACPZ Discontinuation 28/Feb/2012
标准包装: 1
系列: DecDriver™
显示器类型: LCD
接口: 并联
电流 - 电源: 20mA
电源电压: 9 V ~ 18 V
工作温度: 0°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP-VQ(7x7)
包装: 托盘
产品目录页面: 798 (CN2011-ZH PDF)
AD8383
THERMAL VIA STRUCTURE DESIGN
Effective heat transfer from the top to the inner and bottom
layers of the PCB requires thermal vias incorporated into the
thermal pad design. Thermal performance increases logarithmi-
REFERENCE PCB DESIGN
The top copper layer is shown in Figure 13.
7 mm
cally with the number of vias, as shown in Figure 12. With the
AD8383 on a standard JEDEC PCB, θ JA reaches its specified
value when a total of 16 vias are used. At a via count above 36,
θ JA approaches its optimum value as the slope of the curve
approaches zero.
32
30
28
26
Figure 13. Recommended PCB Landing
24
The bottom thermal pad forms AVCC plane.
22
0
10
20
30
40
Thermal Pads
Top PCB Layer:
5.25 mm × 5.25 mm
NUMBER OF VIAS
Figure 12. Thermal Performance vs. Number of Vias (on a JEDEC PCB)
Near optimum thermal performance of production PCBs is
attained when the number of vias is at least 36.
SOLDER MASKING
To minimize the formation of solder voids due to solder flowing
into the via holes (solder wicking), the via diameter should be
Bottom PCB Layer:
Thermal via structure
Diameter:
Number of vias:
Via Grid Pitch:
Miscellaneous
Perimeter Pads:
Solder Mask Swell:
5.25 mm × 5.25 mm
0.25 mm
41
0.5 mm
0.5 mm × 0.25 mm
0.02 mm
small. Solder masking of the via holes on the top layer of the
PCB plugs the via holes, inhibiting solder flow into the holes. To
optimize the thermal pad coverage, the solder mask diameter
should be no more than 0.1 mm larger than the via diameter.
Rev. 0 | Page 11 of 16
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