参数资料
| 型号： | AD8383ACPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC DECIMATING LCD DRIVER 48LFCSP |
| 产品变化通告： | AD8383ACPZ Discontinuation 28/Feb/2012 |
| 标准包装： | 1 |
| 系列： | DecDriver™ |
| 显示器类型： | LCD |
| 接口： | 并联 |
| 电流 - 电源： | 20mA |
| 电源电压： | 9 V ~ 18 V |
| 工作温度： | 0°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 48-LFCSP-VQ（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 798 (CN2011-ZH PDF) |
AD8383
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
NC 1
DB0 2
DB1 3
DB2 4
DB3 5
DB4 6
DB5 7
DB6 8
DB7 9
DB8 10
DB9 11
NC 12
PIN 1
INDICATOR
AD8383
TOP VIEW
7mm × 7mm
(Not to Scale)
36 VID0
35 AVCC0,1
34 VID1
33 AGND1,2
32 VID2
31 AVCC2,3
30 VID3
29 AGND3,4
28 VID4
27 AVCC4,5
26 VID5
25 AGND5
NC = NO CONNECT
Figure 2. 48-Lead LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin Name
DB(0:9)
CLK
STSQ
R/L
E/O
XFR
VID0–VID5
V1, V2
VREFHI,
VREFLO
INV
DVCC
DGND
AVCCx
AGNDx
BYP
STBY
Function
Data Input
Clock
Start Sequence
Right/Left Select
Even/Odd Select
Data Transfer
Analog Outputs
Reference Voltages
Full-Scale References
Invert
Digital Power Supply
Digital Supply Return
Analog Power Supplies
Analog Supply Returns
Bypass
Standby
Description
10-Bit Data Input. MSB = DB(0:9).
Clock Input.
The state of STSQ is detected on the active edge of CLK. A new data loading sequence begins on
the next active edge of CLK after STSQ is detected HIGH.
The active CLK edge is the rising edge when E/O is held HIGH. It is the falling edge when E/O is
held LOW.
A new data loading sequence begins on the left with Channel 0 when this input is LOW, and on
the right with Channel 5 when this input is HIGH.
The active CLK edge is the rising edge when this input is held HIGH and the falling edge when
this input is held LOW. Data is loaded sequentially on the rising edges of CLK when this input is
HIGH and on the falling edges when this input is LOW.
XFR is detected and a data transfer is initiated on a rising CLK edge when this input is held HIGH.
Data is transferred to the video outputs on the next rising CLK edge after XFR is detected.
These pins are directly connected to the analog inputs of the LCD panel.
The voltage applied between these pins set the reference levels of the analog outputs.
The voltage applied between these pins sets the full-scale output voltage.
When this pin is HIGH, the analog output voltages are above VMID. When LOW, the analog
output voltages are below VMID. VMID is a hypothetical reference level set by the voltages
applied to V1 and V2. VMID is equal to (V1 + V2)/2.
Digital Power Supply.
This pin is normally connected to the analog ground plane.
Analog Power Supplies.
Analog Supply Returns.
A 0.1 μF capacitor connected between this pin and AGND ensures optimum settling time.
When HIGH, the internal circuits are debiased and the power dissipation drops to a minimum.
Rev. 0 | Page 6 of 16
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| AD8384 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 6-Channel Decimating LCD DecDriver-R with Level Shifters |
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| AD8385ASVZ | 制造商:Analog Devices 功能描述: |
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