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| 型号： | AD8522AR-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/8页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 12BIT 5V 14-SOIC |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 产品变化通告： | AD8522 Redesign Change 29/Nov/2010 Product Discontinuance 27/Oct/2011 |
| 标准包装： | 2,500 |
| 设置时间： | 16µs |
| 位数： | 12 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 单电源 |
| 功率耗散（最大）： | 25mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 14-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 14-SO |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电压，单极 |
| 采样率（每秒）： | 62.5k |
AD8522–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS
Parameter
Symbol
Condition
Min
Typ
Max
Units
STATIC PERFORMANCE
Resolution
1
N
12
Bits
Relative Accuracy
INL
-1.5
±0.5
+1.5
LSB
Differential Nonlinearity
DNL
Monotonic
-1
±0.5
+1
LSB
Zero-Scale Error
VZSE
Data = 000H
+0.5
+3
mV
Full-Scale Voltage
2
VFS
Data = FFFH
4.079
4.095
4.111
Volts
Full-Scale Tempco2, 3
TCVFS
±15
ppm/
°C
MATCHING PERFORMANCE
Linearity Matching Error
V
FSA/B
±1
LSB
ANALOG OUTPUT
Output Current
IOUT
Data = 800H,
V
OUT
≤ 3 LSB
±5mA
Load Regulation at Half-Scale
LDREG
RL = 402
to ∞, Data = 800
H
1
3
LSB
Capacitive Load
3
CL
No Oscillation
500
pF
REFERENCE OUTPUT
Output Voltage
VREF
2.484
2.500
2.516
V
Output Source Current4
IREF
V
REF < 18 mV
5
mA
Line Rejection
LNREJ
0.025
0.08
%/V
Load Regulation
LDREG
IREF = 0 to 5 mA, Data = 800H
0.025
0.1
%/mA
LOGIC INPUTS & OUTPUTS
Logic Input Low Voltage
VIL
0.8
V
Logic Input High Voltage
VIH
2.4
V
Input Leakage Current
IIL
10
A
Input Capacitance
3
CIL
10
pF
Logic Output Voltage Low
VOL
IOL = 1.6 mA
0.4
V
Logic Output Voltage High
VOH
IOH = 400
A
3.5
V
TIMING SPECIFICATIONS
3, 5
Clock Width High
tCH
35
ns
Clock Width Low
tCL
35
ns
Load Pulse Width
tLDW
25
ns
Data Setup
tDS
10
ns
Data Hold
tDH
20
ns
Clear Pulse Width
tCLRW
20
ns
Load Setup
tLD1
10
ns
Load Hold
tLD2
10
ns
Select
tCSS
30
ns
Deselect
tCSH
30
ns
Clock to SDO Propagation Delay
tPD
20
45
80
ns
AC CHARACTERISTICS
3, 5
Voltage Output Settling Time
6
tS
To
±1 LSB of Final Value
16
s
Crosstalk
CT
Signal Measured at DAC Output,
While Changing Opposite LDA/B
38
dB
DAC Glitch
Q
Half-Scale Transition
13
nV s
Digital Feedthrough
DFT
Signal Measured at DAC Output,
While Changing Data Without LDA/B
2
nV s
SUPPLY CHARACTERISTICS
Positive Supply Current
IDD
VDD = 5.5 V, VIH = 2.4 V or VIL = 0.8 V
3
5
mA
VDD = 5 V, VIL = 0 V
1
2
mA
Power Dissipation
7
PDISS
VDD = 5 V, VIH = 2.4 V or VIL = 0.8 V
15
25
mW
VDD = 5 V, VIL = 0 V
5
10
mW
Power Supply Sensitivity
PSS
V
DD =
±5%
0.002
0.004
%/%
NOTES
11 LSB = 1 mV for 0 V to +4.095 V output range.
2Includes internal voltage reference error.
3These parameters are guaranteed by design and not subject to production testing.
4Very little sink current is available at the V
REF pin. Use external buffer if setting up a virtual ground.
5All input control signals are specified with t
r = tf = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
6The settling time specification does not apply for negative going transitions within the last 6 LSBs of ground. Some devices exhibit double the typical settling time in this 6 LSB region.
7Power Dissipation is calculated I
DD × 5 V.
Specifications subject to change without notice.
(@ VDD = +5.0 V
10%, RL = No Load, –40 C
≤ T
A
≤ +85 C, both DACs tested, unless
otherwise noted)
REV. A
–2–
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