参数资料
型号: AD8522AR-REEL
厂商: Analog Devices Inc
文件页数: 6/8页
文件大小: 0K
描述: IC DAC DUAL 12BIT 5V 14-SOIC
产品培训模块: Data Converter Fundamentals
DAC Architectures
产品变化通告: AD8522 Redesign Change 29/Nov/2010
Product Discontinuance 27/Oct/2011
标准包装: 2,500
设置时间: 16µs
位数: 12
数据接口: 串行
转换器数目: 2
电压电源: 单电源
功率耗散(最大): 25mW
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 14-SOIC(0.154",3.90mm 宽)
供应商设备封装: 14-SO
包装: 带卷 (TR)
输出数目和类型: 2 电压,单极
采样率(每秒): 62.5k
AD8522
input register and transferring the 12 bits of data into the de-
coded address determined by the address bits A and B in the se-
rial input register.
Unipolar Output Operation
This is the basic mode of operation for the AD8522. The
AD8522 has been designed to drive loads as low as 820
in
parallel with 500 pF. The code table for this operation is shown
in Table III.
Table III. Unipolar Code Table
Hexadecimal
Decimal
Analog
Number in
Output
DAC Register
Voltage (V)
FFF
4095
+4.095
801
2049
+2.049
800
2048
+2.048
7FF
2047
+2.047
000
0
5
2
0
1
3
4
10
100
100k
10k
1k
RL TIED TO AGND
DATA = FFFH
VDD = +5V
TA = +25
°C
RL TIED TO +5V
DATA = 000H
LOAD RESISTANCE –
OUTPUT
VOLTAGE
Volts
VINH = +5V
VINL = 0V
Figure 6. Output Swing vs. Load
80
60
40
20
0
–20
–40
–60
–80
123
OUTPUT VOLTAGE – Volts
OUTPUT
CURRENT
mA
DATA = 800H
POSITIVE
CURRENT
LIMIT
NEGATIVE
CURRENT
LIMIT
Figure 9. IOUT vs. VOUT
5.2
5.0
4.8
4.6
4.4
4.2
4.0
0.01
0.1
100
10
1.0
OUTPUT LOAD CURRENT – mA
V
DD
MIN
Volts
VFS ≤ 1 LSB
DATA = FFFH
TA = +25°C
PROPER OPERATION
WHEN VDD SUPPLY
VOLTAGE IS ABOVE
CURVE
Figure 7. Minimum Supply Voltage
vs. Load Current
100
90
10
0%
200V/DIV
100s/DIV
TA = +25°C
NBW = 1MHz
Figure 10. Broadband Noise
1
10
1000
100
1
0.1
10
0.01
+85
°C
–55
°C
+25
°C
VDD = +5V
DATA = 000H
VIH = 5.0V
VIL = 0.0V
OUTPUT SINK CURRENT – A
OUTPUT
PULL-DOWN
VOLTAGE
mV
Figure 8. Pull-Down Voltage vs. Out-
put Sink Current Capability
9
8
7
6
5
4
3
2
1
0
01
3
4
5
2
VDD = +4.5V
VDD = +5V
TA = +25°C
SUPPLY
CURRENT
I
DD
mA
LOGIC INPUT VOLTAGE VINH – Volts
Figure 11. Supply Current vs. Logic
Input Voltage
Typical Performance Characteristics
is possible down to +4.3 V. The minimum operating supply
voltage versus load current plot, in Figure 7, provides informa-
tion for operation below VDD = +4.5 V.
TIMING AND CONTROL
The AD8522 has a 16-bit serial input register that accepts
clocked in data when the CS pin is active low. The DAC regis-
ters are updated by the Load Enable (LDA and LDB) pins.
The AD8522 offers two modes of data loading. The first mode,
hardware-load, directs the data currently clocked into the serial
shift register into either the DAC A or the DAC B register or
both depending on the external active low strobing of the LDA
or LDB pin. Serial data register bit Sf/Hd must be low for this
mode to be in effect.
The second mode of operation is software-load which is de-
signed to minimize the number of control lines connected to
the AD8522. In this mode of operation the LDA and LDB pins
act as one control input taking the present contents of the serial
–6–
REV. A
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