- 您现在的位置：买卖IC网 > PDF目录373958 > AD9070BR (ANALOG DEVICES INC) 10-Bit, 100 MSPS A/D Converter PDF资料下载
参数资料
| 型号： | AD9070BR |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | ADC |
| 英文描述： | 10-Bit, 100 MSPS A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PDSO28 |
| 封装： | PLASTIC, SOIC-28 |
| 文件页数： | 9/16页 |
| 文件大小： | 254K |
| 代理商： | AD9070BR |
AD9070
–
9
–
REV. B
APPLICATION NOTES
Theory of Operation
The AD9070 employs a two-step subranging architecture with
digital error correction.
The sampling and conversion process is initiated by a rising
edge at the ENCODE input. The analog input signal is
buffered by a high speed differential amplifier and applied to a
track-and-hold (T/H) circuit that captures the value of the
input at the sampling instant and maintains it for the duration
of the conversion.
The coarse quantizer (ADC) produces a five-bit estimate of the
input value. Its digital output is reconverted to analog form by
the reconstruction DAC and subtracted from the input signal in
the SUM AMP. The second stage quantizer generates a six-bit
representation of the difference signal. The eleven bits are
presented to the ENCODE LOGIC, which corrects for range
overlap errors and produces an accurate ten-bit result.
Data are strobed to the output on the rising edge of the ENCODE
input, with the data from sample N appearing on the output
following ENCODE rising edge N+3.
USING THE AD9070
ENCODE Input
Any high speed A/D converter is extremely sensitive to the quality
of the sampling clock provided by the user. A Track/Hold circuit is
essentially a mixer, and any noise, distortion or timing jitter on
the clock will be combined with the desired signal at the A/D
output. For that reason, considerable care has been taken in the
design of the ENCODE input of the AD9070 and the user is
advised to give commensurate thought to the clock source.
The ENCODE input is fully differential and may be operated in
a differential or a single-ended mode. It has a common-mode
range of –1 V to –3 V, and is easily driven by a differential ECL
driver. Proper termination at the A/D is important.
AD9070
10k
1k
ENCODE
ENCODE
V
EE
–
5V
GND
R
T
0.1 F
3k
0.1 F
CLK
IN
(1Vp-p)
–
5V
Figure 17. Single-Ended ENCODE: AC Coupled
In single-ended mode, the
ENCODE
input must be tied to an
appropriate reference voltage, generally midway between the
high and the low levels of the incoming logic signal. Many ECL
circuits provide a V
BB
reference voltage intended for this
purpose. If a reference voltage is produced by dividing the
power supply voltage, any noise on the supply used will couple
to the clock input and then to the output data. This is not
recommended. A better approach is to develop the required
voltage from the internal or external converter voltage reference
(VREF OUT).
Very small timing errors can reduce the performance of an A/D
dramatically. Total jitter of only 3.2 ps will limit the perfor-
mance of an A/D sampling a full-scale 50 MHz signal to nine
effective bits. The AD9070’s specified aperture jitter of 2.5 ps
leaves only 2.0 ps of jitter budget for the clock source (an RSS
calculation).
The cleanest clock source is only a crystal oscillator producing a
pure sine wave. In this configuration, or with any roughly
symmetrical clock input, the input can be ac coupled and biased
to a reference voltage that also provides the
ENCODE
input
(Figure 17). This ensures that the reference voltage is centered
on the ENCODE signal.
Digital Outputs
The digital outputs are compatible with 10K ECL logic. The
suggested pull-down is 100
to –2 V. However, to reduce
power consumption, higher value pull-down resistors can be
used when driving very low capacitance loads or at reduced
encode rates. The falling edge slew rate of the output bits will be
degraded with higher value pull-down resistors.
Analog Input
The analog input to the AD9070 is a differential amplifier, but
the design has been optimized for a single-ended input. The
AIN
input should be connected or bypassed to the ground
reference of the input signal. For best dynamic performance,
impedances at AIN and
AIN
should match.
The circuit in Figure 18 illustrates a simple ac-coupled inter-
face. The midscale input voltage and the
AIN
levels are both
provided by the internal reference (VREF OUT).
AD9070
ENCODE
ENCODE
V
EE
–
5V
GND
500
0.1 F
R
T
ENCODE
ENCODE
V
IN
1Vp-p
AIN
AIN
VREF OUT
VREF IN
(MSB) D9
510
(OR 100 TO
–
2V)
D9
–
5V
(LSB) D0
510
(OR 100 TO
–
2V)
D0
–
5V
COMP
REF
BYPASS
0.1 F
500
0.1 F
0.1 F
Figure 18. AD9070 in
–
5 V (ECL) Environment
相关PDF资料 |
PDF描述 |
|---|---|
| AD9071 | 10-Bit, 100 MSPS A/D Converter |
| AD9071BR | 10-Bit, 100 MSPS A/D Converter |
| AD9100AD | Ultrahigh Speed Monolithic Track-and-Hold |
| AD9100JD | Ultrahigh Speed Monolithic Track-and-Hold |
| AD9100SD | Ultrahigh Speed Monolithic Track-and-Hold |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9070BR-REEL | 制造商:Analog Devices 功能描述:ADC Single 100Msps 10-bit Parallel 28-Pin SOIC T/R 制造商:Rochester Electronics LLC 功能描述:- Tape and Reel |
| AD9070TD | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 10-Bit |
| AD9071 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 100 MSPS A/D Converter |
| AD9071/PCB | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 100 MSPS A/D Converter |
| AD90717 | 制造商:Analog Devices 功能描述:- Trays |
发布紧急采购，3分钟左右您将得到回复。