参数资料
| 型号： | AD9115BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 36/52页 |
| 文件大小： | 0K |
| 描述： | IC DAC DUAL 10BIT LO PWR 40LFCSP |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| 位数： | 10 |
| 数据接口： | 串行 |
| 转换器数目： | 2 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 232mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP-VQ（6x6） |
| 包装： | 托盘 |
| 输出数目和类型： | 4 电流，单极 |
| 采样率（每秒）： | 125M |
| 产品目录页面： | 785 (CN2011-ZH PDF) |
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Data Sheet
AD9114/AD9115/AD9116/AD9117
Rev. C | Page 41 of 52
3
2
1
0
D-FF
4
D-FF
OR
DCLKIO-INT
CLKIN-INT
DB[n:0]
(INPUT)
TO DAC CORE
IOUT
DE
L
AY
1
DELAY2
DE
L
AY
1
R
E
T
IM
E
R-
CL
K
IE
OE
DCLKIO
(INPUT/OUTPUT)
CLKIN
(INPUT)
NOTES
D-FFs:
0: RISING OR FALLING EDGE
TRIGGERED FOR I OR Q DATA.
1, 2, 3, 4: RISING EDGE TRIGGERED.
RETIMER-CLK
07
46
6-
05
6
NOTES:
1. DB[n:0], WHERE n IS 7 FOR THE AD9114, 9 FOR THE AD9115, 11 FOR THE AD9116, AND 13 FOR THE AD9117.
Figure 94. Simplified Diagram of AD9114/AD9115/AD9116/AD9117 Timing
DIGITAL DATA LATCHING AND RETIMER SECTION
The AD9114/AD9115/AD9116/AD9117 have two clock inputs,
DCLKIO and CLKIN. The CLKIN is the analog clock whose
jitter affects DAC performance, and the DCLKIO is a digital clock
from an FPGA that needs to have a fixed relationship with the
input data to ensure that the data is sampled correctly by the
flip-flops on the pads.
Figure 94 is a simplified diagram of the entire data capture
system in the AD9114/AD9115/AD9116/AD9117. The double
data rate input data (DB[n:0], where n is 7 for the AD9114, is 9
for the AD9115, is 11 for the AD9116, and 13 for the AD9117) is
latched at the pads/pins either on the rising edge or the falling edge
of the DCLKIO-INT clock, as determined by IRISING, Bit 4 of
SPI Address 0x02. Bit 5 of SPI Address 0x02, IFIRST, determines
which channel data is latched first (that is, I or Q). The captured
data is then retimed to the internal clock (CLKIN-INT) in the
retimer block before being sent to the final analog DAC core
(D-FF 4), which controls the current steering output switches. All
delay blocks depicted in Figure 94 are non-inverting, and any wires
without an explicit delay block can be assumed to have no delay.
Only one channel is shown in Figure 94 with the data pads
(DB[n:0], where n is 7 for the AD9114, is 9 for the AD9115, is
11 for the AD9116, and 13 for the AD9117) serving as double
data rate pads for both channels.
The default PINMD and SPI settings are IE = high (closed) and
OE = low (open). These settings are enabled when RESET/PINMD
(Pin 35) is held high. In this mode, the user has to supply both
DCLKIO and CLKIN. In PINMD, it is also recommended that the
DCLKIO and the CLKIN be in phase for proper functioning of
the DAC, which can easily be ensured by tying the pins together
on the PCB. If the user can access the SPI, setting Bit 2 of SPI
Address 0x02, DCI_EN, to logic low causes the CLKIN to be
used as the DCLKIO also.
Setting Bit 1 or Bit 0 of SPI Address 0x02, DCOSGL or DCODBL,
to logic high allows the user to get a DCLKIO output from the
CLKIN input for use in the user’s PCB system.
It is strongly recommended that DCI_EN = DCOSGL = high,
or DCI_EN = DCODBL = high not be used, even though the
device may appear to function correctly. Similarly, DCOSGL
and DCODBL should not be set to logic high simultaneously.
Retimer
The AD9114/AD9115/AD9116/AD9117 have an internal data
retimer circuit that compares the CLKIN-INT and DCLKIO-INT
clocks and, depending on their phase relationship, selects a
retimer clock (RETIMER-CLK) to safely transfer data from the
DCLKIO used at the chip’s input interface to the CLKIN used to
clock the analog DAC cores (D-FF 4).
The retimer selects one of the three phases shown in Figure 95.
The retimer is controlled by the CLKMODE SPI bits as is
shown in Table 15.
1/2 PERIOD
1/4 PERIOD
1/2 PERIOD
DATA
CLOCK
RETIMER-CLKs
180°
90°
270°
07
46
6-
0
57
Figure 95. RETIMER-CLK Phases
Note that, in most cases, more than one retimer phase works
and, in such cases, the retimer arbitrarily picks one phase that
works. The retimer cannot pick the best or safest phase. If the
user has a working knowledge of the exact phase relationship
between DCLKIO and CLKIN (and thus DCLKIO-INT and
CLKIN-INT because the delay is approximately the same for
both clocks and equal to DELAY1), then the retimer can be
forced to this phase with CLKMODEN = 1, as described in
Table 15 and the following paragraphs.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9115BCPZRL7 | 功能描述:IC DAC DUAL 10BIT LO PWR 40LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 标准包装:47 系列:- 设置时间:2µs 位数:14 数据接口:并联 转换器数目:1 电压电源:单电源 功率耗散（最大）:55µW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:28-SSOP（0.209"，5.30mm 宽） 供应商设备封装:28-SSOP 包装:管件 输出数目和类型:1 电流，单极；1 电流，双极 采样率（每秒）:* |
| AD9115-DPG2-EBZ | 功能描述:IC DAC DUAL 10BIT LO PWR 40LFCSP RoHS:是 类别:编程器，开发系统 >> 评估板 - 数模转换器 (DAC) 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1 系列:- DAC 的数量:4 位数:12 采样率（每秒）:- 数据接口:串行，SPI? 设置时间:3µs DAC 型:电流/电压 工作温度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9115-EBZ | 制造商:Analog Devices 功能描述:DUAL 10 BIT LOW POWER CONVERTER - Boxed Product (Development Kits) |
| AD9116 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual, 8-/10-/12-/14-Bit Low Power Digital-to-Analog Converters |
| AD9116BCPZ | 功能描述:IC DAC DUAL 12BIT LO PWR 40LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
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