参数资料
型号: AD9204BCPZRL7-65
厂商: Analog Devices Inc
文件页数: 18/36页
文件大小: 0K
描述: IC ADC 10BIT 65MSPS 64LFCSP
标准包装: 750
位数: 10
采样率(每秒): 65M
数据接口: 串行,SPI?
转换器数目: 2
功率耗散(最大): 128.5mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
输入数目和类型: 4 个单端,单极;2 个差分,单极
AD9204
Rev. 0 | Page 25 of 36
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR from the low fre-
quency SNR (SNRLF) at a given input frequency (fINPUT) due to
jitter (tJRMS) can be calculated by
SNRHF = 10 log[(2π × fINPUT × tJRMS)2 + 10
]
)
10
/
(
LF
SNR
In the previous equation, the rms aperture jitter represents
the clock input jitter specification. Input frequency (IF)
undersampling applications are particularly sensitive to jitter,
as illustrated in Figure 56.
80
75
70
65
60
55
50
45
1
10
100
1k
FREQUENCY (MHz)
S
NR
(
d
BF
S
)
0.5ps
0.2ps
0.05ps
1.0ps
1.5ps
2.0ps
2.5ps
3.0ps
0
812
2-
0
22
Figure 56. SNR vs. Input Frequency and Jitter
The clock input should be treated as an analog signal in cases in
which aperture jitter may affect the dynamic range of the AD9204.
To avoid modulating the clock signal with digital noise, keep
power supplies for clock drivers separate from the ADC output
driver supplies. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or another method), it should be
retimed by the original clock at the last step.
See the AN-501 Application Note and the AN-756 Application
Note available on www.analog.com for more information.
POWER DISSIPATION AND STANDBY MODE
As shown in Figure 57, the analog core power dissipated by
the AD9204 is proportional to its sample rate. The digital
power dissipation of the CMOS outputs is determined primarily
by the strength of the digital drivers and the load
on each output bit.
The maximum DRVDD current (IDRVDD) can be calculated as
IDRVDD = VDRVDD × CLOAD × fCLK × N
where N is the number of output bits (30, in the case of the
AD9204).
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the Nyquist
frequency of fCLK/2. In practice, the DRVDD current is estab-
lished by the average number of output bits switching, which
is determined by the sample rate and the characteristics of the
analog input signal.
Reducing the capacitive load presented to the output drivers can
minimize digital power consumption. The data in Figure 57 was
taken using the same operating conditions as those used in the
output driver.
140
120
100
80
60
50
0
10
20
30
40
50
60
70
80
CLOCK RATE (MSPS)
ANAL
O
G
CO
R
E
P
O
W
E
R
(
m
W
)
08
12
2-
05
1
130
110
90
70
AD9204-80
AD9204-65
AD9204-40
AD9204-20
Figure 57. AD9204 Analog Core Power vs. Clock Rate
相关PDF资料
PDF描述
MS3106E24-9P CONN PLUG 2POS STRAIGHT W/PINS
MS3106E22-22PY CONN PLUG 4POS STRAIGHT W/PINS
CS5560-ISZR IC ADC 24BIT DELTA-SIGMA 24-SSOP
AD7739BRUZ-REEL7 IC ADC 24BIT 8CH SIG-DEL 24TSSOP
AD9223ARSZ-REEL IC ADC 12BIT 3.0MSPS 28SSOP
相关代理商/技术参数
参数描述
AD9204BCPZRL7-80 功能描述:IC ADC 10BIT 80MSPS 64LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1,000 系列:- 位数:12 采样率(每秒):300k 数据接口:并联 转换器数目:1 功率耗散(最大):75mW 电压电源:单电源 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC(0.295",7.50mm 宽) 供应商设备封装:24-SOIC 包装:带卷 (TR) 输入数目和类型:1 个单端,单极;1 个单端,双极
AD9208BBPZRL-3000
AD9211 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter
AD9211_07 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 200 MSPS/250 MSPS/300 MSPS, 1.8 V Analog-to-Digital Converter
AD9211-170EB 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 170/200/250 MSPS 1.8 V A/D Converter