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参数资料
| 型号： | AD9212ABCPZRL7-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/56页 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT SRL 65MSPS 64LFCSP |
| 标准包装： | 750 |
| 位数： | 10 |
| 采样率（每秒）： | 65M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 833mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 16 个单端，单极；8 个差分，单极 |
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Data Sheet
AD9212
Rev. E | Page 35 of 56
Addr.
(Hex)
Parameter Name
(MSB)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
(LSB)
Bit 0
Default
Value
(Hex)
Notes/
Comments
14
output_mode
X
0 = LVDS
ANSI-644
(default)
1 = LVDS
low power,
(IEEE 1596.3
similar)
X
Output
invert
1 = on
0 = off
(default)
00 = offset binary
(default)
01 = twos complement
0x00
Configures the
outputs and the
format of the data.
15
output_adjust
X
Output driver
termination
00 = none (default)
01 = 200 Ω
10 = 100 Ω
11 = 100 Ω
X
DCO and
FCO
2× drive
strength
1 = on
0 = off
(default)
0x00
Determines
LVDS or other
output properties.
Primarily func-
tions to set the
LVDS span and
common-mode
levels in place of
an external
resistor.
16
output_phase
X
0011 = output clock phase adjust
(0000 through 1010)
0000 = 0° relative to data edge
0001 = 60° relative to data edge
0010 = 120° relative to data edge
0011 = 180° relative to data edge (default)
0101 = 300° relative to data edge
0110 = 360° relative to data edge
1000 = 480° relative to data edge
1001 = 540° relative to data edge
1010 = 600° relative to data edge
1011 to 1111 = 660° relative to data edge
0x03
On devices that
utilize global
clock divide,
this register
determines
which phase
of the divider
output is used
to supply the
output clock.
Internal latching
is unaffected.
19
user_patt1_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-defined
pattern, 1 LSB.
1A
user_patt1_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 1 MSB.
1B
user_patt2_lsb
B7
B6
B5
B4
B3
B2
B1
B0
0x00
User-defined
pattern, 2 LSB.
1C
user_patt2_msb
B15
B14
B13
B12
B11
B10
B9
B8
0x00
User-defined
pattern, 2 MSB.
21
serial_control
LSB first
1 = on
0 = off
(default)
X
<10
MSPS,
low
encode
rate
mode
1 = on
0 = off
(default)
000 = 10 bits (default, normal bit
stream)
001 = 8 bits
010 = 10 bits
011 = 12 bits
100 = 14 bits
0x00
Serial stream
control. Default
causes MSB first
and the native
bit stream
(global).
22
serial_ch_stat
X
Channel
output
reset
1 = on
0 = off
(default)
Channel
power-
down
1 = on
0 = off
(default)
0x00
Used to power
down individual
sections of a
converter (local).
1 X = an undefined feature
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9212BCPZ-40 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 40Msps 10-bit Serial 64-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10BIT ADC 40/65MSPS 1.8V SMD 制造商:Analog Devices 功能描述:IC, 10BIT ADC, 40/65MSPS, 1.8V, SMD |
| AD9212BCPZ-65 | 制造商:Analog Devices 功能描述:ADC Octal Pipelined 65Msps 10-bit Serial 64-Pin LFCSP EP |
| AD9212BCPZRL7-40 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9212BCPZRL7-65 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal, 10-Bit, 40/65 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9214 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 65/80/105 MSPS 3 V A/D Converter |
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