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参数资料
| 型号： | AD9252ABCPZRL7-50 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/52页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT SRL 50MSPS 64LFCSP |
| 标准包装： | 750 |
| 位数： | 14 |
| 采样率（每秒）： | 50M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 8 |
| 功率耗散（最大）： | 773mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 64-LFCSP-VQ（9x9） |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 16 个单端，单极；8 个差分，单极 |
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Data Sheet
AD9252
Rev. E | Page 21 of 52
By asserting the PDWN pin high, the AD9252 is placed into
power-down mode. In this state, the ADC typically dissipates
11 mW. During power-down, the LVDS output drivers are placed
into a high impedance state. The AD9252 returns to normal
operating mode when the PDWN pin is pulled low. This pin is
both 1.8 V and 3.3 V tolerant.
In power-down mode, low power dissipation is achieved by
shutting down the reference, reference buffer, PLL, and biasing
networks. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in the power-down
mode: shorter cycles result in proportionally shorter wake-up
times. With the recommended 0.1 F and 4.7 F decoupling
capacitors on REFT and REFB, approximately 1 sec is required
to fully discharge the reference buffer decoupling capacitors and
approximately 375 s is required to restore full operation.
There are several other power-down options available when
using the SPI. The user can individually power down each
channel or put the entire device into standby mode. The latter
option allows the user to keep the internal PLL powered when
fast wake-up times (~600 ns) are required. See the Memory
Map section for more details on using these features.
Digital Outputs and Timing
The AD9252 differential outputs conform to the ANSI-644 LVDS
standard by default upon power-up. This can be changed to a low
power, reduced signal option (similar to the IEEE 1596.3 standard)
via the SDIO/ODM pin or the SPI. This LVDS standard can further
reduce the overall power dissipation of the device by approximately
36 mW. See the SDIO/ODM Pin section or Table 16 in the
Memory Map section for more information. The LVDS driver
current is derived on chip and sets the output current at each
output equal to a nominal 3.5 mA. A 100 differential termination
resistor placed at the LVDS receiver inputs results in a nominal
350 mV swing at the receiver.
The AD9252 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs for superior switching
performance in noisy environments. Single point-to-point net
topologies are recommended with a 100 termination resistor
placed as close to the receiver as possible. If there is no far-end
receiver termination or there is poor differential trace routing,
timing errors may result. To avoid such timing errors, it is
recommended that the trace length be no longer than 24 inches
and that the differential output traces be kept close together and
at equal lengths. An example of the FCO and data stream when
the AD9252 is used with traces of proper length and position is
shown in Figure 47.
CH1 500mV/DIV = FCO
CH2 500mV/DIV = DCO
CH3 500mV/DIV = DATA
5.0ns/DIV
06296-
027
Figure 47. LVDS Output Timing Example in ANSI-644 Mode (Default)
An example of the LVDS output using the ANSI-644 standard
(default) data eye and a time interval error (TIE) jitter histogram
with trace lengths less than 24 inches on standard FR-4 material
is shown in Figure 48. Figure 49 shows an example of the trace
length exceeding 24 inches on standard FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is the user’s
responsibility to determine if the waveforms meet the timing
budget of the design when the trace lengths exceed 24 inches.
Additional SPI options allow the user to further increase the
internal termination (increasing the current) of all eight outputs
in order to drive longer trace lengths (see Figure 50). Even though
this produces sharper rise and fall times on the data edges and
is less prone to bit errors, the power dissipation of the DRVDD
supply increases when this option is used. In addition, notice in
Figure 50 that the histogram has improved.
In cases that require increased driver strength to the DCO± and
FCO± outputs because of load mismatch, Register 0x15 allows
the user to increase the drive strength by 2×. To do this, first
set the appropriate bit in Register 0x05. Note that this feature
cannot be used with Bit 4 and Bit 5 in Register 0x15. Bit 4 and
Bit 5 take precedence over this feature. See the Memory Map
section for more details.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9252BCPZ-50 | 制造商:Analog Devices 功能描述:IC ((NW)) 制造商:Analog Devices 功能描述:IC,A/D CONVERTER,OCTAL,14-BIT,LLCC,64PIN |
| AD9252BCPZRL7-50 | 制造商:AD 制造商全称:Analog Devices 功能描述:Octal, 14-Bit, 50 MSPS Serial LVDS 1.8 V A/D Converter |
| AD9253 | 制造商:AD 制造商全称:Analog Devices 功能描述:Quad, 14-Bit, 80 MSPS/105 MSPS/125 MSPS |
| AD9253-125EBZ | 功能描述:BOARD EVAL FOR AD9253-125 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
| AD9253BCPZ-105 | 功能描述:IC ADC 14BIT SRL 105MSPS 48LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 其它有关文件:TSA1204 View All Specifications 标准包装:1 系列:- 位数:12 采样率（每秒）:20M 数据接口:并联 转换器数目:2 功率耗散（最大）:155mW 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-TQFP 供应商设备封装:48-TQFP（7x7） 包装:Digi-Reel® 输入数目和类型:4 个单端，单极；2 个差分，单极 产品目录页面:1156 (CN2011-ZH PDF) 其它名称:497-5435-6 |
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