参数资料
型号: AD9252ABCPZRL7-50
厂商: Analog Devices Inc
文件页数: 22/52页
文件大小: 0K
描述: IC ADC 14BIT SRL 50MSPS 64LFCSP
标准包装: 750
位数: 14
采样率(每秒): 50M
数据接口: 串行,SPI?
转换器数目: 8
功率耗散(最大): 773mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 带卷 (TR)
输入数目和类型: 16 个单端,单极;8 个差分,单极
Data Sheet
AD9252
Rev. E | Page 29 of 52
MEMORY MAP
READING THE MEMORY MAP TABLE
Each row in the memory map register table (Table 16) has eight
address locations. The memory map is divided into three sections:
the chip configuration register map (Address 0x00 to Address 0x02),
the device index and transfer register map (Address 0x04,
Address 0x05, and Address 0xFF), and the ADC functions register
map (Address 0x08 to Address 0x22).
The leftmost column of the memory map indicates the register
address number; the default value is shown in the second right-
most column. The Bit 7 column is the start of the default
hexadecimal value given. For example, Address 0x09, the clock
register, has a default value of 0x01, meaning Bit 7 = 0, Bit 6 = 0,
Bit 5 = 0, Bit 4 = 0, Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or
0000 0001 in binary. This setting is the default for the duty cycle
stabilizer in the on condition. By writing 0 to Bit 0 of this address
followed by writing 0x01 in Register 0xFF (transfer bit), the duty
cycle stabilizer turns off. It is important to follow each writing
sequence with a transfer bit to update the SPI registers. All
registers, except Register 0x00, Register 0x04, Register 0x05, and
Register 0xFF, are buffered with a master-slave latch and require
writing to the transfer bit. For more information on this and
other functions, consult the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
RESERVED LOCATIONS
Undefined memory locations should not be written to except
when writing the default values suggested in this data sheet.
Addresses that have values marked as 0 should be considered
reserved and have 0 written to their registers during power-up.
DEFAULT VALUES
When the AD9252 comes out of a reset, critical registers are
preloaded with default values. These values are indicated in
Table 16, where an X refers to an undefined feature.
LOGIC LEVELS
An explanation of various registers follows: “bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
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