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| 型号： | AD9280ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 7/24页 |
| 文件大小： | 0K |
| 描述： | IC ADC CMOS 8BIT 32MSPS 28-SSOP |
| 产品变化通告： | AD9280 Pin Configuration Description Change 21/Apr/2010 |
| 标准包装： | 47 |
| 位数： | 8 |
| 采样率（每秒）： | 32M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 110mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 28-SSOP |
| 包装： | 管件 |
| 输入数目和类型： | 1 个单端，单极 |
| 产品目录页面： | 780 (CN2011-ZH PDF) |
AD9280
–15–
DIFFERENTIAL INPUT OPERATION
The AD9280 will accept differential input signals. This function
may be used by shorting REFTS and REFBS and driving them
as one leg of the differential signal (the top leg is driven into
AIN). In the configuration below, the AD9280 is accepting a
1 V p-p signal. See Figure 29.
AIN
REFTS
REFTF
REFBF
REFBS
AD9280
0.1 F 10 F
0.1 F
2V
1V
AVDD/2
VREF
REFSENSE
MODE
AVDD/2
0.1 F
1.0 F
Figure 29. Differential Input
AD876-8 MODE OF OPERATION
The AD9280 may be dropped into the AD876-8 socket. This
will allow AD876-8 users to take advantage of the reduced
power consumption realized when running the AD9280 on a
3.0 V analog supply.
Figure 30 shows the pin functions of the AD876-8 and AD9280.
The grounded REFSENSE pin and floating MODE pin effec-
tively put the AD9280 in the external reference mode. The
external reference input for the AD876-8 will now be placed
on the reference pins of the AD9280.
The clamp controls will be grounded by the AD876-8 socket.
The AD9280 has a 3 clock cycle delay compared to a 3.5 cycle
delay of the AD876-8.
4V
2V
0.1 F
AVDD
10 F
0.1 F
4V
2V
AIN
REFTS
REFTF
REFBF
REFBS
CLAMP
REFSENSE
AD9280
MODE
NC
CLAMPIN
OTR
VREF
0.1 F
Figure 30. AD876 Mode
CLOCK INPUT
The AD9280 clock input is buffered internally with an inverter
powered from the AVDD pin. This feature allows the AD9280
to accommodate either +5 V or +3.3 V CMOS logic input sig-
nal swings with the input threshold for the CLK pin nominally
at AVDD/2.
The pipelined architecture of the AD9280 operates on both
rising and falling edges of the input clock. To minimize duty
cycle variations the recommended logic family to drive the clock
input is high speed or advanced CMOS (HC/HCT, AC/ACT)
logic. CMOS logic provides both symmetrical voltage threshold
levels and sufficient rise and fall times to support 32 MSPS
operation. The AD9280 is designed to support a conversion rate
of 32 MSPS; running the part at slightly faster clock rates may
be possible, although at reduced performance levels. Conversely,
some slight performance improvements might be realized by
clocking the AD9280 at slower clock rates.
tCL
tCH
tC
25ns
DATA 1
DATA
OUTPUT
INPUT
CLOCK
ANALOG
INPUT
S1
S2
S3
S4
Figure 31. Timing Diagram
The power dissipated by the output buffers is largely propor-
tional to the clock frequency; running at reduced clock rates
provides a reduction in power consumption.
DIGITAL INPUTS AND OUTPUTS
Each of the AD9280 digital control inputs, THREE-STATE
and STBY are reference to analog ground. The clock is also
referenced to analog ground.
The format of the digital output is straight binary (see Figure
32). A low power mode feature is provided such that for STBY
= HIGH and the clock disabled, the static power of the AD9280
will drop below 5 mW.
OTR
–FS+1LSB
–FS
+FS
+FS–1LSB
Figure 32. Output Data Format
HIGH
IMPEDANCE
tDHZ
tDEN
THREE-
STATE
DATA
(D0–D9)
Figure 33. Three-State Timing Diagram
REV. E
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相关代理商/技术参数 |
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| AD9280ARSZRL | 功能描述:IC ADC 8BIT CMOS 32MSPS 28SSOP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:2,500 系列:- 位数:16 采样率（每秒）:15 数据接口:MICROWIRE?，串行，SPI? 转换器数目:1 功率耗散（最大）:480µW 电压电源:单电源 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:38-WFQFN 裸露焊盘 供应商设备封装:38-QFN（5x7） 包装:带卷 (TR) 输入数目和类型:16 个单端，双极；8 个差分，双极 配用:DC1011A-C-ND - BOARD DELTA SIGMA ADC LTC2494 |
| AD9280-EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9280 - Bulk |
| AD9280JRS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 8-Bit |
| AD9280JRSRL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Analog-to-Digital Converter， 8-Bit |
| AD9281 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual Channel 8-Bit Resolution CMOS ADC |
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