- 您现在的位置：买卖IC网 > PDF目录16425 > AD9398/PCBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9398 PDF资料下载
参数资料
| 型号： | AD9398/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9398 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 已用 IC / 零件： | AD9398 |
| 已供物品： | 板 |
| 相关产品： | AD9398KSTZ-100-ND - IC INTERFACE 100MHZ HDMI 100LQFP AD9398KSTZ-150-ND - IC INTERFACE 150MHZ HDMI 100LQFP |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页当前第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页
AD9398
Rev. 0 | Page 25 of 44
2-WIRE SERIAL CONTROL REGISTER DETAILS
CHIP IDENTIFICATION
0x00—Bits[7:0] Chip Revision
An 8-bit value that reflects the current chip revision.
0x11—Bit[7] HSYNC Source
0 = HSYNC, 1 = SOG. The power-up default is 0. These
selections are ignored if Register 0x11, Bit 6 = 0.
0x11—Bit[6] HSYNC Source Override
0 = auto HSYNC source, 1 = manual HSYNC source. Manual
HSYNC source is defined in Register 0x11, Bit 7. The power-up
default is 0.
0x11—Bit[5] VSYNC Source
0 = VSYNC, 1 = VSYNC from SOG. The power-up default is 0.
These selections are ignored if Register 0x11, Bit 4 = 0.
0x11—Bit[4] VSYNC Source Override
0 = auto VSYNC source, 1 = manual VSYNC source. Manual
VSYNC source is defined in Register 0x11, Bit 5. The power-up
default is 0.
0x11—Bit[3] Channel Select
0 = Channel 0, 1 = Channel 1. The power-up default is 0. These
selections are ignored if Register 0x11, Bit 2 = 0.
0x11—Bit[2] Channel Select Override
0 = auto channel select, 1 = manual channel select. Manual
channel select is defined in Register 0x11, Bit 3. The power-up
default is 0.
0x11—Bit[1] Interface Select
0 = analog interface, 1 = digital interface. The power-up default
is 0. These selections are ignored if Register 0x11, Bit 0 = 0.
0x11—Bit[0] Interface Select Override
0 = auto interface select, 1 = manual interface select. Manual
interface select is defined in Register 0x11, Bit 1. The power-up
default is 0.
0x12—Bit[7] Input HSYNC Polarity
0 = active low, 1 = active high. The power-up default is 1. These
selections are ignored if Register 10x2, Bit 6 = 0.
0x12—Bit[6] HSYNC Polarity Override
0 = auto HSYNC polarity, 1 = manual HSYNC polarity.
Manual HSYNC polarity is defined in Register 0x11, Bit 7.
The power-up default is 0.
0x12—Bit[5] Input VSYNC Polarity
0 = active low, 1 = active high. The power-up default is 1. These
selections are ignored if Register 0x11, Bit 4 = 0.
0x12—Bit[4] VSYNC Polarity Override
0 = auto VSYNC polarity, 1 = manual VSYNC polarity. Manual
VSYNC polarity is defined in Register 0x11, Bit 5. The power-
up default is 0.
0x17—Bits[3:0] HSYNCs per VSYNC MSBs
The 4 MSBs of the 12-bit counter that reports the number of
HSYNCs/VSYNC on the active input. This is useful in
determining the mode and aid in setting the PLL divide ratio.
0x18—Bit[7:0] HSYNCs per VSYNC LSBs
The 8 LSBs of the 12-bit counter that reports the number of
HSYNCs/VSYNC on the active input.
0x21—Bit[5] VSYNC Filter Enable
The purpose of the VSYNC filter is to guarantee the position of
the VSYNC edge with respect to the HSYNC edge and to
generate a field signal. The filter works by examining the
placement of VSYNC and regenerating a correctly placed
VSYNC one line later. The VSYNC is first checked to see
whether it occurs in the Field 0 position or the Field 1 position.
This is done by checking the leading edge position against the
sync separator threshold and the HSYNC position. The HSYNC
width is divided into four quadrants with Quadrant 1 starting at
the HSYNC leading edge plus a sync separator threshold. If the
VSYNC leading edge occurs in Quadrant 1 or Quadrant 4, the
field is set to 0 and the output VSYNC is placed coincident with
the HSYNC leading edge. If the VSYNC leading edge occurs in
Quadrant 2 or Quadrant 3, the field is set to 1 and the output
VSYNC leading edge is placed in the center of the line. In this
way, the VSYNC filter creates a predictable relative position
between HSYNC and VSYNC edges at the output.
If the VSYNC occurs near the HSYNC edge, this guarantees
that the VSYNC edge follows the HSYNC edge. This performs
filtering also in that it requires a minimum of 64 lines between
VSYNCs. The VSYNC filter cleans up extraneous pulses that
might occur on the VSYNC. This should be enabled whenever
the HSYNC/VSYNC count is used. Setting this bit to 0 disables
the VSYNC filter. Setting this bit to 1 enables the VSYNC filter.
Power-up default is 0.
0x21—Bit[4] VSYNC Duration Enable
This enables the VSYNC duration block which is designed to
be used with the VSYNC filter. Setting the bit to 0 leaves the
VSYNC output duration unchanged; setting the bit to 1 sets the
VSYNC output duration based on Register 0x22. The power-up
default is 0.
0x22—Bits[7:0] VSYNC Duration
This is used to set the output duration of the VSYNC, and is
designed to be used with the VSYNC filter. This is valid only if
Register 0x21, Bit 4 is set to 1. Power-up default is 4.
相关PDF资料 |
PDF描述 |
|---|---|
| REC8-2415SRWZ/H3/A/M | CONV DC/DC 8W 24VIN 15VOUT |
| GBC15DREH-S93 | CONN EDGECARD 30POS .100 EYELET |
| A1KXB-1636M | IDC CABLE - APK16B/AE16M/X |
| UPA0J122MPD6TD | CAP ALUM 1200UF 6.3V 20% RADIAL |
| AD9889B/PCBZ | KIT EVALUATION FOR AD9889B |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9410 | 制造商:AD 制造商全称:Analog Devices 功能描述:10-Bit, 210 MSPS A/D Converter |
| AD9410/PCB | 制造商:Analog Devices 功能描述:EVAL BOARD FOR AD9410 - Bulk |
| AD9410BSQ | 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 10-bit Parallel 80-Pin LQFP EP 制造商:Analog Devices 功能描述:ADC SGL FLASH 210MSPS 10-BIT PARALLEL 80LQFP EP - Trays 制造商:Analog Devices 功能描述:IC 10-BIT ADC |
| AD9410BSQZ | 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 10-bit Parallel 80-Pin LQFP EP 制造商:Analog Devices 功能描述:ADC SGL FLASH 210MSPS 10-BIT PARALLEL 80LQFP EP - Trays |
| AD9410BSVZ | 功能描述:IC ADC 10BIT 210MSPS 80-TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:250 系列:- 位数:12 采样率（每秒）:1.8M 数据接口:并联 转换器数目:1 功率耗散（最大）:1.82W 电压电源:模拟和数字 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-LQFP 供应商设备封装:48-LQFP（7x7） 包装:管件 输入数目和类型:2 个单端，单极 |
发布紧急采购，3分钟左右您将得到回复。