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参数资料
| 型号： | AD9398/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/44页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9398 |
| 标准包装： | 1 |
| 主要目的： | 视频，视频处理 |
| 已用 IC / 零件： | AD9398 |
| 已供物品： | 板 |
| 相关产品： | AD9398KSTZ-100-ND - IC INTERFACE 100MHZ HDMI 100LQFP AD9398KSTZ-150-ND - IC INTERFACE 150MHZ HDMI 100LQFP |
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AD9398
Rev. 0 | Page 16 of 44
Hex Address
Read/Write
or Read
Only
Bits
Default
Value
Register Name
Description
[4]
***0****
BT656 EN
Enables EAV/SAV codes to be inserted into the video
output data.
[3]
****0***
Force DE Generation
Allows use of the internal DE generator in DVI mode.
[2:0]
*****000
Interlace Offset
Sets the difference (in HSYNCs) in field length between
Field 0 and Field 1.
0x28
Read/Write
[7:2]
011000**
VS Delay
Sets the delay (in lines) from the VSYNC leading edge to
the start of active video.
[1:0]
******01
HS Delay MSB
MSB, Register 0x29.
0x29
Read/Write
[7:0]
00000100
HS Delay
Sets the delay (in pixels) from the HSYNC leading edge
to the start of active video.
0x2A
Read/Write
[3:0]
****0101
Line Width MSB
MSB, Register 0x2B.
0x2B
Read/Write
[7:0]
00000000
Line Width
Sets the width of the active video line in pixels.
0x2C
Read/Write
[3:0]
****0010
Screen Height MSB
MSB, Register 0x2D.
0x2D
Read/Write
[7:0]
11010000
Screen Height
Sets the height of the active screen in lines.
0x2E
Read/Write
[7]
0*******
Ctrl EN
Allows Ctrl [3:0] to be output on the I2S data pins.
00 = I2S mode.
[6:5]
*00*****
I2S Out Mode
01 = right-justified.
10 = left-justified.
11 = raw IEC60958 mode.
[4:0]
***11000
I2S Bit Width
Sets the desired bit width for right-justified mode.
0x2F
Read
[6]
*0******
TMDS Sync Detect
Detects a TMDS DE.
[5]
**0*****
TMDS Active
Detects a TMDS clock.
[4]
***0****
AV Mute
Gives the status of AV mute based on general control
packets.
[3]
****0***
HDCP Keys Read
Returns 1 when read of EEPROM keys is successful.
[2:0]
*****000
HDMI Quality
Returns quality number based on DE edges.
0x30
Read
[6]
*0******
HDMI Content
Encrypted
This bit is high when HDCP decryption is in use (content
is protected). The signal goes low when HDCP is not
being used. Use this bit to allow copying of the content.
The bit should be sampled at regular intervals because it
can change on a frame-by-frame basis.
[5]
**0*****
DVI HSYNC Polarity
Returns DVI HSYNC polarity.
[4]
***0****
DVI VSYNC Polarity
Returns DVI VSYNC polarity.
[3:0]
****0000
HDMI Pixel Repetition
Returns current HDMI pixel repetition amount. 0 = 1×,
1 = 2×, ... The clock and data outputs automatically
de-repeat by this value.
0x31
Read/Write
[7:4]
1001****
MV Pulse Max
Sets the maximum pseudo sync pulse width for
Macrovision detection.
[3:0]
****0110
MV Pulse Min
Sets the minimum pseudo sync pulse width for
Macrovision detection.
0x32
Read/Write
[7]
0*******
MV Oversample En
Tells the Macrovision detection engine whether
oversampling occurs.
[6]
*0******
MV Pal En
Tells the Macrovision detection engine to enter PAL
mode.
[5:0]
**001101
MV Line Count Start
Sets the start line for Macrovision detection.
0x33
Read/Write
[7]
1*******
MV Detect Mode
0 = standard definition.
1 = progressive scan mode.
[6]
*0******
MV Settings Override
0 = use hard-coded settings for line counts and pulse
widths.
1 = use I2C values for these settings.
[5:0]
**010101
MV Line Count End
Sets the end line for Macrovision detection.
0x34
Read/Write
[7:6]
10******
MV Pulse Limit Set
Sets the number of pulses required in the last 3 lines
(SD mode only).
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