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| 型号： | AD9480ASUZ-250 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | IC ADC 8BIT 250MSPS 3.3V 44TQFP |
| 标准包装： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 250M |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 590mW |
| 电压电源： | 单电源 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 44-TQFP |
| 供应商设备封装： | 44-TQFP（10x10） |
| 包装： | 托盘 |
| 输入数目和类型： | 2 个单端，单极；2 个差分，单极 |
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AD9480
Rev. A | Page 18 of 28
External Reference
An external reference can be used for greater accuracy and
temperature stability when required. The gain of the AD9480
can also be varied using this configuration. A voltage output
DAC can be used to set VREF, providing for a means to digitally
adjust the full-scale voltage. VREF can be externally set to
voltages from 0.75 V to 1.5 V; optimum performance is typically
obtained at VREF = 1 V. (See the Typical Performance
Characteristics section.)
04619-
018
MAY REQUIRE
RC FILTER
AVDD
EXTERNAL
REFERENCE OR
DAC INPUT
VREF
SENSE
Figure 38. External Reference
Programmable Reference
The programmable reference can be used to set a differential
input span anywhere between 0.75 V p-p and 1.5 V p-p by
using an external resistor divider. The sense pin will self-bias to
0.5 V, and the resulting VREF is equal to 0.5 × (1 + R1/R2). It is
recommended to keep the sum of R1 + R2 ≥ 10 k to limit
VREF loading (for VREF = 1.5 V, set R1 equal to 7 k and R2
equal to 3.5 k).
04619-019
0.1
F
R1
R2
10
F
VREF
SENSE
Figure 39. Programmable Reference
DIGITAL OUTPUTS
LVDS outputs are available when a 3.7 k RSET resistor is
placed at Pin 42 (LVDSBIAS) to ground. The RSET resistor
current (~1.2 V/RSET) is ratioed on-chip, setting the output
current at each output equal to a nominal 3.5 mA with an RSET
of 3.74 k. Varying the RSET current also linearly changes the
LVDS output current, resulting in a variable output swing for a
fixed termination resistance.
A 100 differential termination resistor placed at the LVDS
receiver inputs results in a nominal 350 mV swing at the
receiver. LVDS mode facilitates interfacing with LVDS receivers
in custom ASICs and FPGAs that have LVDS capability for
superior switching performance in noisy environments. Single
point-to-point net topologies are recommended with a 100
termination resistor as close to the receiver as possible. Keep the
trace length 3 inches to 4 inches maximum and the differential
output trace lengths as equal as possible.
OUTPUT CODING
Table 10.
Code
(VIN+) (VIN)
Offset Binary
Twos Complement
255
>+0.512 V
1111 1111
0111 1111
255
+0.512 V
1111 1111
0111 1111
254
+0.508 V
1111 1110
0111 1110
129
+0.004 V
1000 0001
0000 0001
128
+0.0 V
1000 0000
0000 0000
127
–0.004 V
0111 1111
1111 1111
2
0.504 V
0000 0010
1000 0010
1
0.508 V
0000 0001
1000 0001
0
0.512 V
0000 0000
1000 0000
0
<0.512 V
0000 0000
1000 0000
INTERLEAVING TWO AD9480s
Instrumentation applications may prefer to interleave or ping-
pong two AD9480s to achieve twice the sample rate, or
500 MSPS. In these applications, it is important to match the
gain and offset of the two ADCs. Varying the reference voltage
allows the gain of the ADCs to be adjusted; external dc offset
compensation can be used to reduce offset mismatch between
two ADCs. The sampling phase offset between the two ADCs is
extremely important as well and requires very low skew
between clock signals driving the ADCs (<2 ps clock skew for a
100 MHz analog input frequency).
DATA CLOCK OUT
An LVDS data clock is available at DCO+ and DCO. These
clocks can facilitate latching off-chip, providing a low skew
clocking solution. The on-chip delay of the DCO clocks tracks
with the on-chip delay of the data bits (under similar loading),
such that the variation between TPD and TCPD is minimized. It is
recommended to keep the trace lengths on the data and DCO
pins matched and to 3 inches to 4 inches maximum. The output
and DCO outputs should be designed for a differential
characteristic impedance of 100 and terminated differentially
at the receiver with 100 .
POWER-DOWN
The chip can be placed in a low power state by driving the
PDWN pin to logic high. Typical power-down dissipation is
15 mW. The data outputs and DCO outputs are high impedance
in power-down state. The time it takes to go into power-down
from assertion of PDWN is one cycle; recovery from power-
down is accomplished in three cycles.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9480ASUZ-2501 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9480BSU-250 | 制造商:Analog Devices 功能描述:ADC SGL PIPELINED 250MSPS 8BIT PARALLEL 44TQFP - Bulk |
| AD9480BSUZ-250 | 功能描述:IC ADC 8BIT 250MSPS 3.3V 44TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9480BSUZ-2501 | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 250 MSPS 3.3 V A/D Converter |
| AD9480-LVDS/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9480 制造商:Analog Devices 功能描述:8 BIT 250 MSPS 3V ADC PB FREE EB - Bulk |
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