参数资料
型号: AD9480ASUZ-250
厂商: Analog Devices Inc
文件页数: 4/28页
文件大小: 0K
描述: IC ADC 8BIT 250MSPS 3.3V 44TQFP
标准包装: 1
位数: 8
采样率(每秒): 250M
数据接口: 并联
转换器数目: 1
功率耗散(最大): 590mW
电压电源: 单电源
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 44-TQFP
供应商设备封装: 44-TQFP(10x10)
包装: 托盘
输入数目和类型: 2 个单端,单极;2 个差分,单极
AD9480
Rev. A | Page 12 of 28
SFDR
SNR
SINAD
SAMPLE CLOCK (MHz)
dB
75
70
65
60
55
50
45
40
0
50
150
200
100
250
300
04619-
026
Figure 10. SNR, SINAD, SFDR vs. Sample Clock Frequency, AIN = 70 MHz @ 1 dBFS
ANALOG INPUT DRIVE LEVEL (dBFS)
dB
80
60
70
40
50
20
30
0
10
–70
–60
–40
–50
–30
–20
–10
0
04619-
027
SFDRdBFS
SFDRdBc
65dB
REF LINE
Figure 11. SFDR vs. AIN Input Level; AIN = 70 MHz @ 250 MSPS
MHz
dB
0
–20
–10
–50
–40
–30
–70
–60
–90
–80
060
40
20
80
100
120
04619-
028
F1, F2 = –7dBFS
2F2-F1 = –71.1dBc
2F1-F2 = –68dBc
Figure 12. Two-Tone Intermodulation Distortion
(69.3 MHz and 70.3 MHz; fS = 250 MSPS)
ENCODE (MSPS)
CURRENT
IN
mA
180
160
100
120
140
60
40
20
80
0
50
100
200
250
150
300
04619-
029
IAVDD
IDRVDD
Figure 13. IAVDD and IDRVDD vs. Clock Rate, CLOAD = 5 pF AIN = 70 MHz @ –1 dBFS
DCS OFF
DCS ON
CLOCK POSITIVE DUTY CYCLE (%)
dB
50
49
48
47
46
45
43
42
41
44
40
20
30
40
50
60
70
80
046190-
030
Figure 14. SNR, SINAD vs. Clock Pulse Width High,
AIN = 70 MHz @ –1 dBFS, 250 MSPS, DCS On/Off
EXTERNAL VREF VOLTAGE (V)
SNR,
SI
NAD
d
B
50.0
47.5
45.0
42.5
40.0
0.5
1.1
0.9
0.7
1.5
1.3
1.7
1.9
04619-031
SNR
SFDR
50
65
70
75
80
SF
DR
d
B
SINAD
Figure 15. SNR, SINAD, and SFDR vs. VREF in External Reference Mode,
AIN = 70 MHz @ –1 dBFS, 250 MSPS
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