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参数资料
| 型号： | AD9513/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 14/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9513 |
| 设计资源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9513 Eval Brd BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟分配 |
| 已用 IC / 零件： | AD9513 |
| 已供物品： | 板 |
| 相关产品： | AD9513BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9513BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
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AD9513
Rev. 0 | Page 21 of 28
DELAY BLOCK
OUT2 includes an analog delay element that gives variable time
delays (ΔT) in the clock signal passing through that output.
÷N
SELECT
LVDS
CMOS
T
MU
X
OUTPUT
DRIVER
FINE DELAY ADJUST
(16 STEPS)
FULL SCALE : 1.5ns, 5ns, 10ns
CLOCK INPUT
OUT1 ONLY
05595-
025
Figure 25. Analog Delay Block
The amount of delay that can be used is determined by the
output frequency. The amount of delay is limited to less than
one-half cycle of the clock period. For example, for a 10 MHz
clock, the delay can extend to the full 11.6 ns maximum. However,
for a 100 MHz clock, the maximum delay is less than 5 ns (or
half of the period).
The AD9513 allows for the selection of three full-scale delays,
1.8 ns, 6.0 ns, and 11.6 ns, set by delay full-scale (see Table 11).
Each of these full-scale delays can be scaled by 16 fine
adjustment values, which are set by the delay word (see Table 13).
The delay block adds some jitter to the output. This means that
the delay function should be used primarily for clocking digital
chips, such as FPGA, ASIC, DUC, and DDC, rather than for
supplying a sample clock for data converters. The jitter is higher
for longer full scales because the delay block uses a ramp and
trip points to create the variable delay. A longer ramp means
more noise has a chance of being introduced.
When the delay block is OFF (bypassed), it is also powered
down.
OUTPUTS
Each of the three AD9513 outputs can be selected either as
LVDS differential outputs or as pairs of CMOS single-ended
outputs. If selected as CMOS, the OUT is a noninverted, single-
ended output, and OUTB is an inverted, single-ended output.
OUTB
OUT
3.5mA
055
95-
027
Figure 26. LVDS Output Simplified Equivalent Circuit
05
595
-0
28
OUT1/
OUT1B
VS
Figure 27. CMOS Equivalent Output Circuit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9514 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs |
| AD9514/PCB | 制造商:Analog Devices 功能描述:CLOCK DISTRIBUTION - Bulk |
| AD9514/PCBZ | 功能描述:BOARD EVAL CLOCK 3CH AD9514 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:- 主要目的:电信，线路接口单元（LIU） 嵌入式:- 已用 IC / 零件:IDT82V2081 主要属性:T1/J1/E1 LIU 次要属性:- 已供物品:板，电源，线缆，CD 其它名称:82EBV2081 |
| AD9514BCPZ | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9514BCPZ-REEL7 | 功能描述:IC CLOCK DIST 3OUT PLL 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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