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| 型号： | AD9520-3/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 41/80页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD9520-3 |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 已用 IC / 零件： | AD9520-3 |
| 已供物品： | 板 |
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AD9520-3
Data Sheet
Rev. A | Page 46 of 80
Table 36 to Table 39 show the output duty cycle for various configurations of the channel divider and VCO divider.
Table 36. Channel Divider Output Duty Cycle with VCO Divider ≠ 1; Input Duty Cycle Is 50%
VCO Divider
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Even
Channel divider bypassed
50%
Odd = 3
Channel divider bypassed
33.3%
50%
Odd = 5
Channel divider bypassed
40%
50%
Even, odd
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Even, odd
Odd
(N + 1)/(N + M + 2)
50%, requires M = N + 1
Table 37. Channel Divider Output Duty Cycle with VCO Divider ≠ 1; Input Duty Cycle Is X%
VCO Divider
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Even
Channel divider bypassed
50%
Odd = 3
Channel divider bypassed
33.3%
(1 + X%)/3
Odd = 5
Channel divider bypassed
40%
(2 + X%)/5
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Even
Odd
(N + 1)/(N + M + 2)
50%, requires M = N + 1
Odd = 3
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Odd = 3
Odd
(N + 1)/(N + M + 2)
(3N + 4 + X%)/(6N + 9), requires M = N + 1
Odd = 5
Even
(N + 1)/(N + M + 2)
50%, requires M = N
Odd = 5
Odd
(N + 1)/(N + M + 2)
(5N + 7 + X%)/(10N + 15), requires M = N + 1
Table 38. Channel Divider Output Duty Cycle When the VCO Divider Is Enabled and Set to 1
Input Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Any
Even
(N + 1)/(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/(M + N + 2)
(N + 1 + X%)/(2 × N + 3), requires M = N + 1
The channel divider must be enabled when the VCO divider = 1.
Table 39. Channel Divider Output Duty Cycle When the VCO Divider Is Bypassed
Input Clock
Duty Cycle
DX
Output Duty Cycle
N + M + 2
Disable Divider x DCC = 1b
Disable Divider x DCC = 0b
Any
Channel divider bypassed
Same as input duty cycle
Any
Even
(N + 1)/(M + N + 2)
50%, requires M = N
50%
Odd
(N + 1)/(M + N + 2)
50%, requires M = N + 1
X%
Odd
(N + 1)/(M + N + 2)
(N + 1 + X%)/(2 × N + 3), requires M = N + 1
The internal VCO has a duty cycle of 50%. Therefore, when the
VCO is connected directly to the output, the duty cycle is 50%.
If the CLK input is routed directly to the output, the duty cycle of
the output is the same as the CLK input.
Phase Offset or Coarse Time Delay
Each channel divider allows for a phase offset or a coarse time
delay to be programmed by setting register bits (see Table 40).
These settings determine the number of cycles (successive rising
edges) of the channel divider input frequency by which to offset, or
delay, the rising edge of the output of the divider. This delay is
with respect to a nondelayed output (that is, with a phase offset
of zero). The amount of the delay is set by five bits loaded into
the phase offset (PO) register plus the start high (SH) bit for
each channel divider.
When the start high bit is set, the delay is also affected by the
number of low cycles (M) programmed for the divider.
The SYNC function must be used to make phase offsets effective
(see the Synchronizing the Outputs—SYNC Function section).
Table 40. Setting Phase Offset and Division
Divider
Start
High
(SH) Bits
Phase
Offset
(PO) Bits
Low Cycles,
MValue Bits
High Cycles,
N Value Bits
0
0x191[4]
0x191[3:0]
0x190[7:4]
0x190[3:0]
1
0x194[4]
0x194[3:0]
0x193[7:4]
0x193[3:0]
2
0x197[4]
0x197[3:0]
0x196[7:4]
0x196[3:0]
3
0x19A[4]
0x19A[3:0]
0x199[7:4]
0x199[3:0]
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