参数资料
型号: AD9514/PCBZ
厂商: Analog Devices Inc
文件页数: 1/28页
文件大小: 0K
描述: BOARD EVAL CLOCK 3CH AD9514
设计资源: AD9513/14/15 Eval Brd Schematics
AD9513/14/15 Gerber Files
AD9514 Eval Brd BOM
标准包装: 1
主要目的: 计时,时钟分配
已用 IC / 零件: AD9514
已供物品:
相关产品: AD9514BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP
AD9514BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP
1.6 GHz Clock Distribution IC,
Dividers, Delay Adjust, Three Outputs
AD9514
Rev. 0
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rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2005 Analog Devices, Inc. All rights reserved.
FEATURES
1.6 GHz differential clock input
3 programmable dividers
Divide-by in range from1 to 32
Phase select for coarse delay adjust
2 independent 1.6 GHz LVPECL clock outputs
Additive broadband output jitter 225 fs rms
1 independent 800 MHz/250 MHz LVDS/CMOS clock output
Additive broadband output jitter 300 fs rms/290 fs rms
Time delays up to 10 ns
Device configured with 4-level logic pins
Space-saving, 32-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
ATE
FUNCTIONAL BLOCK DIAGRAM
VREF
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
SETUP LOGIC
OUT0
CLK
CLKB
SYNCB
RSET
VS
GND
OUT0B
OUT1
OUT1B
OUT2
OUT2B
AD9514
/1. . . /32
Δt
LVPECL
LVDS/CMOS
05596-
001
Figure 1.
GENERAL DESCRIPTION
The AD9514 features a multi-output clock distribution IC in a
design that emphasizes low jitter and phase noise to maximize
data converter performance. Other applications with demanding
phase noise and jitter requirements also benefit from this part.
There are three independent clock outputs. Two of the outputs
are LVPECL, and the third output can be set to either LVDS or
CMOS levels. The LVPECL outputs operate to 1.6 GHz, and the
third output operates to 800 MHz in LVDS mode and to
250 MHz in CMOS mode.
Each output has a programmable divider that can be set to
divide by a selected set of integers ranging from 1 to 32. The
phase of one clock output relative to another clock output can
be set by means of a divider phase select function that serves as
a coarse timing adjustment.
The LVDS/CMOS output features a delay element with three
selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each
with 16 steps of fine adjustment.
The AD9514 does not require an external controller for
operation or setup. The device is programmed by means of
11 pins (S0 to S10) using 4-level logic. The programming pins
are internally biased to VS. The VREF pin provides a level of
VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.
The AD9514 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9514 is available in a 32-lead LFCSP and operates from
a single 3.3 V supply. The temperature range is 40°C to +85°C.
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