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参数资料
| 型号： | AD9514/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CLOCK 3CH AD9514 |
| 设计资源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9514 Eval Brd BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟分配 |
| 已用 IC / 零件： | AD9514 |
| 已供物品： | 板 |
| 相关产品： | AD9514BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9514BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
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AD9514
Rev. 0 | Page 26 of 28
LVDS CLOCK DISTRIBUTION
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9514 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 40. The
far-end termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing may still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
The AD9514 provides one clock output (OUT2) that is
selectable as either CMOS or LVDS levels. Low voltage
differential signaling (LVDS) is a differential output option for
OUT2. LVDS uses a current mode output stage. The current is
3.5 mA, which yields 350 mV output swing across a 100 Ω
resistor. The LVDS output meets or exceeds all ANSI/TIA/EIA-
644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 38.
50
Ω
10
Ω
OUT2/OUT2B
SELECTED AS CMOS
VS
CMOS
3pF
100
Ω
100
Ω
05596-
034
VS
LVDS
100
Ω
DIFFERENTIAL (COUPLED)
VS
LVDS
100
Ω
05596-
032
Figure 40. CMOS Output with Far-End Termination
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9514 offers both LVPECL and
LVDS outputs that are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
Figure 38. LVDS Output Termination
See Application Note AN-586 at www.analog.com for more
information on LVDS.
CMOS CLOCK DISTRIBUTION
SETUP PINS (S0 TO S10)
The AD9514 provides one output (OUT2) that is selectable as
either CMOS or LVDS levels. When selected as CMOS, this
output provides for driving devices requiring CMOS level logic
at their clock inputs.
The setup pins that require a logic level of VS (internal self-
bias) should be tied together and bypassed to ground via a
capacitor.
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be used.
The setup pins that require a logic level of VS should be tied
together, along with the VREF pin, and bypassed to ground via
a capacitor.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are also limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as important
as the circuit design. Proper RF techniques must be used for
device selection, placement, and routing, as well as power
supply bypassing and grounding to ensure optimum
performance.
10
Ω
MICROSTRIP
GND
5pF
60.4
Ω
1.0 INCH
CMOS
05596-
033
Figure 39. Series Termination of CMOS Output
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9515 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| ad9515/pcb | 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.6 GHZ CLOCK DISTRIBUTION IC, DIVIDERS, DLY AD - Bulk |
| AD9515/PCBZ | 功能描述:BOARD EVAL CLOCK 2CH AD9515 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9515BCPZ | 功能描述:IC CLOCK DIST 2OUT PLL 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9515BCPZ-REEL7 | 功能描述:IC CLOCK DIST 2OUT PLL 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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