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参数资料
| 型号： | AD9514/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL CLOCK 3CH AD9514 |
| 设计资源： | AD9513/14/15 Eval Brd Schematics AD9513/14/15 Gerber Files AD9514 Eval Brd BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟分配 |
| 已用 IC / 零件： | AD9514 |
| 已供物品： | 板 |
| 相关产品： | AD9514BCPZ-ND - IC CLOCK DIST 3OUT PLL 32LFCSP AD9514BCPZ-REEL7-ND - IC CLOCK DIST 3OUT PLL 32LFCSP |
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AD9514
Rev. 0 | Page 18 of 28
FUNCTIONAL DESCRIPTION
OVERALL
The AD9514 provides for the distribution of its input clock
on up to three outputs simultaneously. OUT0 and OUT1 are
LVPECL levels. OUT2 can be set to either LVDS or CMOS
levels. Each output has its own divider that can be set for a
divide ratio selected from a list of integer values from 1
(bypassed) to 32.
OUT2 includes an analog delay block that can be set to add an
additional delay of 1.5 ns, 5 ns, or 10 ns full scale, each with
16 levels of fine adjustment.
CLK, CLKB—DIFFERENTIAL CLOCK INPUT
The CLK and CLKB pins are differential clock input pins.
This input works up to 1600 MHz. The jitter performance is
degraded by a slew rate below 1 V/ns. The input level should be
between approximately 150 mV p-p to no more than 2 V p-p.
Anything greater can result in turning on the protection diodes
on the input pins.
See Figure 23 for the CLK equivalent input circuit. This input
is fully differential and self-biased. The signal should be ac-
coupled using capacitors. If a single-ended input must be used,
this can be accommodated by ac coupling to one side of the
differential input only. The other side of the input should be
bypassed to a quiet ac ground by a capacitor.
2.5k
Ω
5k
Ω
5k
Ω
2.5k
Ω
CLKB
CLK
VS
CLOCK INPUT
STAGE
05596-
021
Figure 23 Clock Input Equivalent Circuit
SYNCHRONIZATION
Power-On SYNC
A power-on sync (POS) is issued when the VS power supply is
turned on to ensure that the outputs start in synchronization.
The power-on sync works only if the VS power supply transi-
tions the region from 2.2 V to 3.1 V within 35 ms. The POS can
occur up to 65 ms after VS crosses 2.2 V. Only outputs which are
not divide = 1 are synchronized.
05596-094
CLK
OUT
0V
3.3V
2.2V
3.1V
VS
CLOCK FREQUENCY
IS EXAMPLE ONLY
DIVIDE = 2
PHASE = 0
< 65ms
INTERNAL SYNC NODE
35ms
MAX
Figure 24. Power-On Sync Timing
SYNCB
If the setup configuration of the AD9514 is changed during
operation, the outputs can become unsynchronized. The
outputs can be re-synchronized to each other at any time.
Synchronization occurs when the SYNCB pin is pulled low and
released. The clock outputs (except where divide = 1) are forced
into a fixed state (determined by the divide and phase settings)
and held there in a static condition until the SYNCB pin is
returned to high. Upon release of the SYNCB pin, after four
cycles of the clock signal at CLK, all outputs continue clocking
in synchronicity (except where divide = 1).
When divide = 1 for an output, that output is not affected by
SYNCB.
05596-
093
CLK
SYNCB
OUT
3 CLK CYCLES
4 CLK CYCLES
EXAMPLE: DIVIDE
≥ 8
PHASE = 0
EXAMPLE DIVIDE
RATIO PHASE = 0
Figure 25. SYNCB Timing with Clock Present
05596-
092
4 CLK CYCLES
CLK
OUT
SYNCB
DEPENDS ON PREVIOUS STATE AND DIVIDE RATIO
§§
§
DEPENDS ON PREVIOUS STATE
EXAMPLE DIVIDE
RATIO PHASE = 0
MIN 5ns
Figure 26. SYNCB Timing with No Clock Present
The outputs of the AD9514 can be synchronized by using the
SYNCB pin. Synchronization aligns the phases of the clock
outputs, respecting any phase offset that has been set on a
particular output’s divider.
SYNCB
05596-
022
Figure 27. SYNCB Equivalent Input Circuit
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9515 | 制造商:AD 制造商全称:Analog Devices 功能描述:1.6 GHz Clock Distribution IC, Dividers, Delay Adjust, Two Outputs |
| ad9515/pcb | 制造商:Analog Devices 功能描述:EVAL KIT FOR 1.6 GHZ CLOCK DISTRIBUTION IC, DIVIDERS, DLY AD - Bulk |
| AD9515/PCBZ | 功能描述:BOARD EVAL CLOCK 2CH AD9515 RoHS:是 类别:编程器，开发系统 >> 评估演示板和套件 系列:- 标准包装:1 系列:PSoC® 主要目的:电源管理，热管理 嵌入式:- 已用 IC / 零件:- 主要属性:- 次要属性:- 已供物品:板，CD，电源 |
| AD9515BCPZ | 功能描述:IC CLOCK DIST 2OUT PLL 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
| AD9515BCPZ-REEL7 | 功能描述:IC CLOCK DIST 2OUT PLL 32LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
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