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| 型号： | AD9520-3/PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 63/80页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD9520-3 |
| 设计资源： | Synchronizing Multiple AD9910 1 GSPS Direct Digital Synthesizers (CN0121) Phase Coherent FSK Modulator (CN0186) AD9520 Eval Brd Schematic AD9520 BOM |
| 标准包装： | 1 |
| 主要目的： | 计时，时钟发生器 |
| 已用 IC / 零件： | AD9520-3 |
| 已供物品： | 板 |
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AD9520-3
Data Sheet
Rev. A | Page 66 of 80
Reg.
Addr.
(Hex) Bits Name
Description
[2:0] Prescaler P Prescaler: DM = dual modulus; FD = fixed divide. Prescaler P is part of the feedback divider. See the VCO/VCXO Feedback Divider
N—P, A, and B section of the datasheet for details.
Bit
2
Bit
1
Bit
0
Mode
Prescaler
0
FD
Divide-by-1.
0
1
FD
Divide-by-2.
0
1
0
DM
Divide-by-2 and divide-by-3 when A ≠ 0; divide-by-2 when A = 0.
0
1
DM
Divide-by-4 and divide-by-5 when A ≠ 0; divide-by-4 when A = 0.
1
0
DM
Divide-by-8 and divide-by-9 when A ≠ 0; divide-by-8 when A = 0.
1
0
1
DM
Divide-by-16 and divide-by-17 when A ≠ 0; divide-by-16 when A = 0.
1
0
DM
Divide-by-32 and divide-by-33 when A ≠ 0; divide-by-32 when A = 0 (default).
1
FD
Divide-by-3.
0x017 [7:2] STATUS
pin control
Selects the signal that appears at the STATUS pin. Register 0x01D[7] must be 0b to reprogram the STATUS pin.
Bit
7
Bit
6
Bit
5
Bit
4
Bit
3
Bit
2
Level or
Dynamic
Signal
Signal at STATUS Pin
0
LVL
Ground (dc) (default).
0
1
DYN
N divider output (after the delay).
0
1
0
DYN
R divider output (after the delay).
0
1
DYN
A divider output.
0
1
0
DYN
Prescaler output.
0
1
0
1
DYN
PFD up pulse.
0
1
0
DYN
PFD down pulse.
0
X
LVL
Ground (dc). Used for all settings of these bits that are not otherwise specified in this table.
The selections that follow are also used for REFMON and LD pin control.
1
0
LVL
Ground (dc).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (N/A in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active high.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active high.
1
0
1
LVL
Status of REF1 frequency; active high.
1
0
1
0
LVL
Status of REF2 frequency; active high.
1
0
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
0
1
LVL
Status of VCO frequency; active high.
1
0
1
0
LVL
Selected reference (low = REF1, high = REF2).
1
0
1
0
1
LVL
DLD; active high.
1
0
1
0
LVL
Holdover active; active high.
1
0
1
LVL
N/A. Do not use.
1
0
LVL
VS (PLL power supply).
1
0
1
DYN
REF1 clock (differential reference when in differential mode).
1
0
1
0
DYN
REF2 clock (not available in differential mode).
1
0
1
DYN
Selected reference to PLL (differential reference when in differential mode).
1
0
1
0
DYN
Unselected reference to PLL (not available when in differential mode).
1
0
1
0
1
LVL
Status of selected reference (status of differential reference); active low.
1
0
1
0
LVL
Status of unselected reference (not available in differential mode); active low.
1
0
1
LVL
Status of REF1 frequency; active low.
1
0
LVL
Status of REF2 frequency; active low.
1
0
1
LVL
(Status of REF1 frequency) AND (status of REF2 frequency).
1
0
1
0
LVL
(DLD) AND (status of selected reference) AND (status of VCO).
1
0
1
LVL
Status of VCO frequency; active low.
1
0
LVL
Selected reference (low = REF2, high = REF1).
1
0
1
LVL
DLD; active low.
1
0
LVL
Holdover active; active low.
1
LVL
N/A. Do not use.
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