参数资料
| 型号： | AD9575ARUZPEC |
| 厂商： | Analog Devices Inc |
| 文件页数： | 3/16页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 16TSSOP |
| 标准包装： | 96 |
| 系列： | PCI Express® (PCIe) |
| 类型： | 扇出缓冲器（分配），网络时钟发生器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 输入： | 晶体 |
| 输出： | LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 312.5MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
AD9575
Rev. A | Page 11 of 16
TERMINOLOGY
Phase Jitter
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0° to 360° for
each cycle. Actual signals, however, display a certain amount of
variation from ideal phase progression over time. This phenom-
enon is called phase jitter. Although many causes can contribute
to phase jitter, one major cause is random noise, which is charac-
terized statistically as Gaussian (normal) in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as
a series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in decibels) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency
is also given.
Phase Noise
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency interval.
Phase noise has a detrimental effect on error rate performance
by increasing eye closure at the transmitter output and reducing
the jitter tolerance/sensitivity of the receiver.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. In a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Because these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
Additive Phase Noise
Additive phase noise is the amount of phase noise that is attrib-
utable to the device or subsystem being measured. The phase
noise of any external oscillators or clock sources is subtracted.
This makes it possible to predict the degree to which the device
affects the total system phase noise when used in conjunction
with the various oscillators and clock sources, each of which
contributes its own phase noise to the total. In many cases, the
phase noise of one element dominates the system phase noise.
Additive Time Jitter
Additive time jitter is the amount of time jitter that is attribut-
able to the device or subsystem being measured. The time jitter
of any external oscillators or clock sources is subtracted. This
makes it possible to predict the degree to which the device affects
the total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contributes
its own time jitter to the total. In many cases, the time jitter of
the external oscillators and clock sources dominates the system
time jitter.
相关PDF资料 |
PDF描述 |
|---|---|
| AD9577BCPZ-R7 | IC CLOCK GENERATOR 40LFCSP |
| AD9600ABCPZ-150 | IC ADC 10BIT 150MSPS 64LFCSP |
| AD9608BCPZRL7-125 | IC ADC 10BIT 125MSPS 64LFCSP |
| AD9609BCPZRL7-80 | IC ADC 10BIT SRL/SPI 80M 32LFCSP |
| AD9613BCPZ-170 | IC ADC 12BIT SRL 170MSPS 64LFCSP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9575-EVALZ-LVD | 制造商:AD 制造商全称:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9575-EVALZ-PEC | 制造商:AD 制造商全称:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9576/PCBZ | 功能描述:DUAL CHANNEL ASYNCHRONOUS EVALUA 制造商:analog devices inc. 系列:* 零件状态:有效 标准包装:1 |
| AD9576BCPZ | 功能描述:DUAL CHANNEL ASYNCHRONOUS CLOCK 制造商:analog devices inc. 系列:* 零件状态:有效 标准包装:1 |
| AD9576BCPZ-REEL7 | 功能描述:DUAL CHANNEL ASYNCHRONOUS CLOCK 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 类型:Clock Generator，Frequency Synthesizer PLL:是 输入:时钟，晶体 输出:CMOS，HCSL，HSTL，LVDS 电路数:1 比率 - 输入:输出:3：11 差分 - 输入:输出:是/是 频率 - 最大值:1.25GHz 分频器/倍频器:是/无 电压 - 电源:2.38 V ~ 3.63 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-WFQFN 裸露焊盘 供应商器件封装:64-LFCSP（9x9） 标准包装:750 |
发布紧急采购，3分钟左右您将得到回复。