参数资料
| 型号： | AD9575ARUZPEC |
| 厂商： | Analog Devices Inc |
| 文件页数： | 5/16页 |
| 文件大小： | 0K |
| 描述： | IC PLL CLOCK GEN 25MHZ 16TSSOP |
| 标准包装： | 96 |
| 系列： | PCI Express® (PCIe) |
| 类型： | 扇出缓冲器（分配），网络时钟发生器 |
| PLL： | 是 |
| 主要目的： | PCI Express（PCIe） |
| 输入： | 晶体 |
| 输出： | LVCMOS，LVDS，LVPECL |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/是 |
| 频率 - 最大： | 312.5MHz |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 管件 |
AD9575
Rev. A | Page 13 of 16
3.3V
50
50
SINGLE-ENDED
(NOT COUPLED)
3.3V
LVPECL
127
127
83
83
08
462-
02
5
VT = VDD – 1.3V
LVPECL
Figure 20. LVPECL Far-End Termination
LVDS CLOCK DISTRIBUTION
The AD9575 is also available with low voltage differential
signaling (LVDS) outputs. LVDS uses a current mode output
stage with a factory programmed current level. The normal
value (default) for this current is 3.5 mA, which yields a 350 mV
output swing across a 100 Ω resistor. The LVDS outputs meet or
exceed all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 21.
50
50
LVDS
100
0
84
62
-0
17
Figure 21. LVDS Output Termination
See the AN-586 Application Note on the Analog Devices
website at www.analog.com for more information about LVDS.
LVCMOS CLOCK DISTRIBUTION
The AD9575 provides a 33.33 MHz or 62.5 MHz clock output,
which is a dedicated LVCMOS level. Whenever single-ended
LVCMOS clocking is used, some of the following general guide-
lines should be followed.
Point-to-point nets should be designed such that a driver has
only one receiver on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver (see
Figure 22). The value of the resistor is dependent on the board
design and timing requirements (typically 10 Ω to 100 Ω is
used). LVCMOS outputs are limited in terms of the capacitive
load or trace length that they can drive. Typically, trace lengths
less than 6 inches are recommended to preserve signal rise/fall
times and preserve signal integrity.
10
MICROSTRIP
GND
5pF
60.4
1.0 INCH
CMOS
084
62
-01
8
Figure 22. Series Termination of LVCMOS Output
Termination at the far end of the PCB trace is a second option.
The LVCMOS output of the AD9575 does not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 23. The far-end
termination network should match the PCB trace impedance
and provide the desired switching point.
The reduced signal swing may still meet receiver input
requirements in some applications. This can be useful when
driving long trace lengths on less critical nets.
50
10
VPULLUP = 3.3V
LVCMOS
3pF
100
100
0
84
62
-0
19
Figure 23. LVCMOS Output with Far-End Termination
TYPICAL APPLICATION CIRCUIT
1
2
3
4
5
6
7
8
VDDA
VDDX
XO1
GNDA
GNDX
XO2
GNDA
VDDA
16
15
14
13
12
11
10
9
GND
LVDS/LVPECL OUT
CMOS OUT/SEL1
GND_CMOS
VDD_CMOS
VDD
SEL0
AD9575
50
RT =
100
50
1nF
0.1F
VS
0.1F
Cx1 = 22pF
Cx2 = 22pF
VS
08
46
2-
02
8
Figure 24. Typical Application Circuit (in LVDS Configuration)
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相关代理商/技术参数 |
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| AD9575-EVALZ-LVD | 制造商:AD 制造商全称:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9575-EVALZ-PEC | 制造商:AD 制造商全称:Analog Devices 功能描述:Network Clock Generator, Two Outputs |
| AD9576/PCBZ | 功能描述:DUAL CHANNEL ASYNCHRONOUS EVALUA 制造商:analog devices inc. 系列:* 零件状态:有效 标准包装:1 |
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| AD9576BCPZ-REEL7 | 功能描述:DUAL CHANNEL ASYNCHRONOUS CLOCK 制造商:analog devices inc. 系列:- 包装:带卷（TR） 零件状态:有效 类型:Clock Generator，Frequency Synthesizer PLL:是 输入:时钟，晶体 输出:CMOS，HCSL，HSTL，LVDS 电路数:1 比率 - 输入:输出:3：11 差分 - 输入:输出:是/是 频率 - 最大值:1.25GHz 分频器/倍频器:是/无 电压 - 电源:2.38 V ~ 3.63 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:64-WFQFN 裸露焊盘 供应商器件封装:64-LFCSP（9x9） 标准包装:750 |
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