参数资料
型号: AD9609-65EBZ
厂商: Analog Devices Inc
文件页数: 1/32页
文件大小: 0K
描述: BOARD EVALUATION AD9609 65MSPS
设计资源: AD9649/29/09 Schematics
AD9649/29/09 Gerber Files
标准包装: 1
ADC 的数量: 1
位数: 10
采样率(每秒): 65M
数据接口: 串行,SPI?
输入范围: 2 Vpp
在以下条件下的电源(标准): 73.3mW @ 65MSPS
工作温度: -40°C ~ 85°C
已用 IC / 零件: AD9609
已供物品:
10-Bit, 20 MSPS/40 MSPS/65 MSPS/80 MSPS,
1.8 V Analog-to-Digital Converter
AD9609
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityis assumedbyAnalogDevicesforitsuse,norforanyinfringementsof patentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
2009 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR
61.5 dBFS at 9.7 MHz input
61.0 dBFS at 200 MHz input
SFDR
75 dBc at 9.7 MHz input
73 dBc at 200 MHz input
Low power
45 mW at 20 MSPS
76 mW at 80 MSPS
Differential input with 700 MHz bandwidth
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.10 LSB
Serial port control options
Offset binary, gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE, CDMA2000, WiMAX, TD-SCDMA
Smart antenna systems
Battery-powered instruments
Handheld scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
PET/SPECT imaging
FUNCTIONAL BLOCK DIAGRAM
SPI
MODE
CONTROLS
DIVIDE
BY
1TO 8
DCS
REF
SELECT
VIN+
VIN–
VREF
SENSE
CLK+ CLK–
AVDD
GND
SDIO SCLK
CSB
PDWN
AD9609
DFS
MODE
D0 (LSB)
DCO
0854
1-
001
D9 (MSB)
OR
CMO
S
O
U
TP
U
T
B
U
FF
E
R
ADC
CORE
PROGRAMMING DATA
VCM
RBIAS
DRVDD
Figure 1.
PRODUCT HIGHLIGHTS
1.
The AD9609 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V to 3.3 V logic families.
2.
The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3.
A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO and data output
(D9 to D0) timing and offset adjustments, and voltage
reference modes.
4.
The AD9609 is packaged in a 32-lead RoHS compliant
LFCSP that is pin compatible with the AD9629 12-bit ADC
and the AD9649 14-bit ADC, enabling a simple migration
path between 10-bit and 14-bit converters sampling from
20 MSPS to 80 MSPS.
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AD9609BCPZ-65 功能描述:IC ADC 10BIT 65MSPS LP 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:microPOWER™ 位数:8 采样率(每秒):1M 数据接口:串行,SPI? 转换器数目:1 功率耗散(最大):- 电压电源:模拟和数字 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:24-VFQFN 裸露焊盘 供应商设备封装:24-VQFN 裸露焊盘(4x4) 包装:Digi-Reel® 输入数目和类型:8 个单端,单极 产品目录页面:892 (CN2011-ZH PDF) 其它名称:296-25851-6
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