参数资料
型号: AD9628BCPZ-105
厂商: Analog Devices Inc
文件页数: 1/44页
文件大小: 0K
描述: IC ADC DUAL 12BIT 64-LFCSP
标准包装: 1
位数: 12
采样率(每秒): 105M
数据接口: LVDS,并联,串行,SPI
转换器数目: 2
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 64-VFQFN 裸露焊盘,CSP
供应商设备封装: 64-LFCSP-VQ(9x9)
包装: 托盘
输入数目和类型: 4 个单端,2 个差分
12-Bit, 125/105 MSPS, 1.8 V Dual
Analog-to-Digital Converter
Rev.
0
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responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2011 Analog Devices, Inc. All rights reserved.
FEATURES
1.8 V analog supply operation
1.8 V CMOS or LVDS outputs
SNR = 71.2 dBFS @ 70 MHz
SFDR = 93 dBc @ 70 MHz
Low power: 74 mW/channel ADC core @ 125 MSPS
Differential analog input with 650 MHz bandwidth
IF sampling frequencies to 200 MHz
On-chip voltage reference and sample-and-hold circuit
2 V p-p differential analog input
DNL = ±0.25 LSB
Serial port control options
Offset binary, Gray code, or twos complement data format
Optional clock duty cycle stabilizer
Integer 1-to-8 input clock divider
Data output multiplex option
Built-in selectable digital test pattern generation
Energy-saving power-down modes
Data clock out with programmable clock and data
alignment
APPLICATIONS
Communications
Diversity radio systems
Multimode digital receivers
GSM, EDGE, W-CDMA, LTE,
CDMA2000, WiMAX, TD-SCDMA
I/Q demodulation systems
Smart antenna systems
Broadband data applications
Battery-powered instruments
Hand-held scope meters
Portable medical imaging
Ultrasound
Radar/LIDAR
1This product is protected by a U.S patent.
FUNCTIONAL BLOCK DIAGRAM
VIN+A
VIN–A
VREF
SENSE
VCM
RBIAS
VIN–B
VIN+B
ORA
D0A
D11A
DCOA
DRVDD
ORB
D11B
D0B
DCOB
SDIO
AGND
AVDD
SCLK
SPI
PROGRAMMING DATA
M
U
X
OP
TION
PDWN DFS
CLK+ CLK–
MODE
CONTROLS
DCS
DUTY CYCLE
STABILIZER
SYNC
DIVIDE
1 TO 8
OEB
CSB
REF
SELECT
ADC
C
MO
S/
L
V
DS
OU
TP
U
T
B
U
FFE
R
ADC
C
MO
S/
L
V
DS
OU
TP
U
T
B
U
FFE
R
AD9628
NOTES
1. PIN NAMES ARE FOR THE CMOS PIN CONFIGURATION ONLY;
SEE FIGURE 7 FOR LVDS PIN NAMES.
09976-
001
Figure 1.
PRODUCT HIGHLIGHTS
1. The AD96281 operates from a single 1.8 V analog power
supply and features a separate digital output driver supply
to accommodate 1.8 V CMOS or LVDS logic families.
2. The patented sample-and-hold circuit maintains excellent
performance for input frequencies up to 200 MHz and is
designed for low cost, low power, and ease of use.
3. A standard serial port interface supports various product
features and functions, such as data output formatting,
internal clock divider, power-down, DCO/data timing and
offset adjustments.
4. The AD9628 is packaged in a 64-lead RoHS-compliant
LFCSP that is pin compatible with the AD9650/AD9269/
AD9268 16-bit ADC, the AD9258/AD9251/AD9648 14-bit
ADCs, the AD9231 12-bit ADC, and the AD9608/AD9204
10-bit ADCs, enabling a simple migration path between
10-bit and 16-bit converters sampling from 20 MSPS to
125 MSPS.
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