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参数资料
| 型号： | AD9644-155KITZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 32/44页 |
| 文件大小： | 0K |
| 描述： | KIT EVAL FOR AD9644 |
| 设计资源： | AD9644 Gerber Files |
| 标准包装： | 1 |
| 系列： | * |
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AD9644
Data Sheet
Rev. C | Page 38 of 44
Addr
(Hex)
Register
Name
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(LSB)
Default
Value
(Hex)
Default/
Comments
0x76
JESD204A
serial reserved
Field 1 (RES1)
Serial Reserved Field 1 (RES1) – these registers are available for customer use
0x00
0x77
JESD204A
serial reserved
Field 2 (RES2)
Serial Reserved Field 2 (RES2) – these registers are available for customer use
0x00
0x78
JESD204A
checksum
value (FCHK)
for Lane 0
(local)
Serial checksum value for Lane 0 (FCHK)
0x00
Read only
0x79
JESD204A
checksum
value (FCHK)
for lane 1
(local)
Serial checksum value for Lane 1 (FCHK)
0x00
Read only
1
The channel index register at Address 0x05 should be set to 0x03 (default) when writing to Address 0x00.
MEMORY MAP REGISTER DESCRIPTIONS
For additional information about functions controlled in
Register 0x00 to Register 0x25, see the AN-877 Application Note,
Interfacing to High Speed ADCs via SPI.
Sync Control (Register 0x3A)
Bits[7:3]—Open
Bit 2—Clock Divider Next Sync Only
If the master sync buffer enable bit (Address 0x3A, Bit 0) and
the clock divider sync enable bit (Address 0x3A, Bit 1) are high, Bit
2 allows the clock divider to sync to the first sync pulse it receives
and to ignore the rest. The clock divider sync enable bit (Address
0x3A, Bit 1) resets after it syncs.
Bit 1—Clock Divider Sync Enable
Bit 1 gates the sync pulse to the clock divider. The sync signal is
enabled when Bit 1 is high and Bit 0 is high. This is continuous
sync mode.
Bit 0—Master Sync Buffer Enable
Bit 0 must be high to enable any of the sync functions. If the
sync capability is not used this bit should remain low to
conserve power.
JESD204A Quick Configure (Register 0x5E)
Bits[7:3]—Reserved
Bits[2:0]—Register Quick Configuration
Writes to Bits[2:0] of this register configure the part for the
most popular modes of operation for the JESD204A link. The
intent of this register is to simplify the part setup for typical
serial link operation modes. Writing values other than 0x0 to
this register causes registers throughout the JESD204A memory
map to be updated. Once these registers have been written the
affected JESD204A configuration register reads back with their
new values and can be updated. These bits are self clearing and
always read back as 0b000.
000: default—configuration determined by other registers
001: two converters using two links with one lane per link
(maximum sample rate = 80 MHz or 155 MHz) Each link
configuration:
M = 1; N’ = 16; CF = 0; K = 16; S = 1; F = 2; L = 1; HD = 0;
010 = two converters using one link with two lanes per link
(Maximum sample rate = 80 MHz or 155 MHz). Each link
configuration:
M = 2; N’ = 16; CF = 0; K = 16; S = 1; F = 2; L = 2; HD = 0;
uses DSYNCA pin for synchronization. Setting this mode sets
Address 0x5F = 0x02 and sets Address 0x60 = 0x14 for Link A
and sets Address 0x60 = 0x01 for Link B.
011 = two converters using one link and a single lane (maxi-
mum sample rate = 78.125 MHz). Each link configuration: M = 2;
N’ = 16; CF = 0; K = 8;S = 1; F = 4; L = 1; HD = 0; uses DSYNCA
pin for synchronization and DOUTA for output signals.
100 to 111: reserved.
JESD204A Lane Assignment (Register 0x5F)
Bits[7:4]—Reserved
Bits[3:0]—JESD204A Serial Lane Control
These bits set the lane usage. See Figure 62.
0000: one lane per link. Link A: Lane 0 sent on Lane A,
Link B: Lane 0 sent on Lane B.
0001: one lane per link. Link A: Lane 0 sent on Lane B,
Link B: Lane 0 sent on Lane A.
0010: two lanes per link. Link A: Lane 0, one sent on Lane A,
Link B disabled.
0011: two lanes per link. Link A: Lane 0, one sent on Lane B,
Lane A. Link B disabled.
0100: two lanes per link. Link B: Lane 0, one sent on Lane A,
Lane B. Link A disabled.
0101: two lanes per link. Link B: Lane 0, one sent on Lane B,
Lane A. Link A disabled.
0110 to 1111: reserved for future use.
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