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| 型号： | AD9649BCPZRL7-65 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC ADC 14BIT 65MSPS 32LFCSP |
| 标准包装： | 1,500 |
| 位数： | 14 |
| 采样率（每秒）： | 65M |
| 数据接口： | 串行，SPI? |
| 转换器数目： | 1 |
| 功率耗散（最大）： | 87.5mW |
| 电压电源： | 模拟和数字 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 32-LFCSP-VQ |
| 包装： | 带卷 (TR) |
| 输入数目和类型： | 2 个单端，单极；1 个差分，单极 |
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AD9649
Rev. 0 | Page 23 of
32
BUILT-IN SELF-TEST (BIST) AND OUTPUT TEST
The AD9649 includes a built-in test feature designed to enable
verification of the integrity of each channel, as well as facilitate
board-level debugging. Also included is a built-in self-test (BIST)
feature that verifies the integrity of the digital datapath of the
AD9649. Various output test options are also provided to place
predictable values on the outputs of the AD9649.
BUILT-IN SELF-TEST (BIST)
The BIST is a thorough test of the digital portion of the selected
AD9649 signal path. Perform the BIST test after a reset to ensure
that the part is in a known state. During the BIST test, data from
an internal pseudorandom noise (PN) source is driven through
the digital datapath of both channels, starting at the ADC block
output. At the datapath output, CRC logic calculates a signature
from the data. The BIST sequence runs for 512 cycles and then
stops. When the BIST sequence is complete, the BIST compares
the signature results with a predetermined value. If the signatures
match, the BIST sets Bit 0 of Register 0x24, signifying that the
test passed. If the BIST test failed, Bit 0 of Register 0x24 is cleared.
The outputs are connected during this test so that the PN sequence
can be observed as it runs. Writing the value 0x05 to Register 0x0E
runs the BIST, enabling Bit 0 (BIST enable) of Register 0x0E
and resetting the PN sequence generator, Bit 2 (BIST init) of
Register 0x0E. Upon completion of the BIST, Bit 0 of Register 0x24
is automatically cleared. The PN sequence can be continued from
its last value by writing a 0 in Bit 2 of Register 0x0E. However, if the
PN sequence is not reset, the signature calculation does not equal
the predetermined value at the end of the test. The user must
then rely on verifying the output data.
OUTPUT TEST MODES
The output test options are described in Table 16 at Address 0x0D.
When an output test mode is enabled, the analog section of the
ADC is disconnected from the digital back end blocks and the
test pattern is run through the output formatting block. Some of
the test patterns are subject to output formatting, and some are
not. The PN generators from the PN sequence tests can be reset
by setting Bit 4 or Bit 5 of Register 0x0D. These tests can be per-
formed with or without an analog signal (if present, the analog
signal is ignored), but they do require an encode clock. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
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相关代理商/技术参数 |
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| AD9649BCPZRL7-80 | 功能描述:IC ADC 14BIT 80MSPS 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模数转换器 系列:- 标准包装:1 系列:- 位数:14 采样率（每秒）:83k 数据接口:串行，并联 转换器数目:1 功率耗散（最大）:95mW 电压电源:双 ± 工作温度:0°C ~ 70°C 安装类型:通孔 封装/外壳:28-DIP（0.600"，15.24mm） 供应商设备封装:28-PDIP 包装:管件 输入数目和类型:1 个单端，双极 |
| AD9649W | 功能描述:IC ADC 制造商:analog devices inc. 系列:* 零件状态:上次购买时间 标准包装:1 |
| AD9649XCPZ-80 | 功能描述:14 Bit Analog to Digital Converter 1 Input 1 Pipelined 32-LFCSP-WQ (5x5) 制造商:analog devices inc. 系列:- 包装:托盘 零件状态:上次购买时间 位数:14 采样率（每秒）:80M 输入数:1 输入类型:差分 数据接口:并联 配置:S/H-ADC 无线电 - S/H:ADC:1:1 A/D 转换器数:1 架构:管线 参考类型:内部 电压 - 电源，模拟:1.7 V ~ 1.9 V 电压 - 电源，数字:1.7 V ~ 3.6 V 特性:- 工作温度:-40°C ~ 85°C 封装/外壳:32-VFQFN 裸露焊盘，CSP 供应商器件封装:32-LFCSP-WQ（5x5） 标准包装:1 |
| AD9650 | 制造商:AD 制造商全称:Analog Devices 功能描述:16-Bit, 25 MSPS/65 MSPS/80 MSPS/105 MSPS, 1.8 V Dual Analog-to-Digital Converter (ADC) |
| AD9650-105EBZ | 功能描述:数据转换 IC 开发工具 16Bit Hi SNR 105 Msps Dual ADC RoHS:否 制造商:Texas Instruments 产品:Demonstration Kits 类型:ADC 工具用于评估:ADS130E08 接口类型:SPI 工作电源电压:- 6 V to + 6 V |
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