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参数资料
| 型号： | AD9734-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 25/72页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9734 |
| 标准包装： | 1 |
| DAC 的数量： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 1.2G |
| 数据接口： | 串行，SPI? |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板，软件 |
| 已用 IC / 零件： | AD9734 |
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AD9734/AD9735/AD9736
Rev. A | Page 31 of 72
FULL SCALE CURRENT (FSC) REGISTERS (REG. 2, REG. 3)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x02
FSC_1
SLEEP
–
FSC<9>
FSC<8>
0x03
FSC_2
FSC<7>
FSC<6>
FSC<5>
FSC<4>
FSC<3>
FSC<2>
FSC<1>
FSC<0>
Table 12. Full Scale Current Output Register Bit Descriptions
Bit Name
Read/Write
Description
SLEEP
WRITE
0, enable DAC output.
1, set DAC output current to 0 mA.
FSC<9:0>
WRITE
0x000, 10 mA full-scale output current.
0x200, 20 mA full-scale output current.
0x3FF, 30 mA full-scale output current.
LVDS CONTROLLER (LVDS_CNT) REGISTERS (REG. 4, REG. 5, REG. 6)
ADDR
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
0x04
LVDS_CNT1
MSD<3>
MSD<2>
MSD<1>
MSD<0>
MHD<3>
MHD<2>
MHD<1>
MHD<0>
0x05
LVDS_CNT2
SD<3>
SD<2>
SD<1>
SD<0>
LCHANGE
ERR_HI
ERR_LO
CHECK
0x06
LVDS_CNT3
LSURV
LAUTO
LFLT<3>
LFLT<2>
LFLT<1>
LFLT<0>
LTRH<1>
LTRH<0>
Table 13. LVDS Controller Register Bit Descriptions
Bit Name
Read/Write
Description
MSD<3:0>
WRITE
0x0, set setup delay for the measurement system.
READ
If ( LAUTO = 1), the latest measured value for the setup delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
MHD<3:0>
WRITE
0x0, set hold delay for the measurement system.
READ
If ( LAUTO = 1), the latest measured value for the hold delay.
If ( LAUTO = 0), readback of the last SPI write to this bit.
SD<3:0>
WRITE
0x0, set sample delay.
READ
If ( LAUTO = 1), the result of a measurement cycle is stored in this register.
If ( LAUTO = 0), readback of the last SPI write to this bit.
LCHANGE
READ
0, no change from previous measurement.
1, change in value from the previous measurement.
NOTE: The average filter and the threshold detection are not applied to this bit.
ERR_HI
READ
One of the 15 LVDS inputs is above the input voltage limits of the IEEE reduced link specification.
ERR_LO
READ
One of the 15 LVDS inputs is below the input voltage limits of the IEEE reduced link specification.
CHECK
READ
0, phase measurement—sampling in the previous or following DATA cycle.
1, phase measurement—sampling in the correct DATA cycle.
LSURV
WRITE
0, the controller stops after completion of the current measurement cycle.
1, continuous measurements are taken and an interrupt is issued if the clock alignment drifts beyond the
threshold value.
LAUTO
WRITE
0, sample delay is not automatically updated.
1, continuously starts measurement cycles and updates the sample delay according to the measurement.
NOTE: LSURV (Reg. 6, Bit 7) must be set to 1 and the LVDS IRQ (Reg. 1, Bit 3) must be set to 0 for AUTO mode.
LFLT<3:0>
WRITE
0x0, average filter length, Delay = Delay + Delta Delay/2^ LFLT <3:0>, values greater than 12 (0x0C) are
clipped to 12.
LTRH<2:0>
WRITE
000, set auto update threshold values.
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相关代理商/技术参数 |
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| AD9734-EB | 制造商:Analog Devices 功能描述:EVAL BD FOR AD9735 DAC, 10-/12-/14BIT, 1200 MSPS DACS - Trays |
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| AD9735BBCRL | 功能描述:IC DAC 12BIT 1.2GSPS 160CSPBGA RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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