参数资料
| 型号： | AD9744ARZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 8/32页 |
| 文件大小： | 0K |
| 描述： | IC DAC 14BIT 210MSPS 28-SOIC |
| 产品培训模块： | Data Converter Fundamentals DAC Architectures |
| 标准包装： | 1,000 |
| 系列： | TxDAC® |
| 设置时间： | 11ns |
| 位数： | 14 |
| 数据接口： | 并联 |
| 转换器数目： | 1 |
| 电压电源： | 模拟和数字 |
| 功率耗散（最大）： | 145mW |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 28-SOIC W |
| 包装： | 带卷 (TR) |
| 输出数目和类型： | 2 电流，单极；2 电流，双极 |
| 采样率（每秒）： | 210M |
| 配用： | AD9744ACP-PCBZ-ND - BOARD EVAL FOR AD9744ACP |
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AD9744
Data Sheet
Rev. C | Page 16 of 32
Figure 29. Clock Termination in PECL Mode
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the relationship
between the position of the clock edges and the time at which
the input data changes. The AD9744 is rising edge triggered,
and so exhibits dynamic performance sensitivity when the data
transition is close to this edge. In general, the goal when applying
the AD9744 is to make the data transition close to the falling
clock edge. This becomes more important as the sample rate
increases. Figure 30 shows the relationship of SFDR to clock
placement with different sample rates. Note that at the lower
sample rates, more tolerance is allowed in clock placement,
while at higher rates, more care must be taken.
Figure 30. SFDR vs. Clock Placement at fOUT = 20 MHz and 50 MHz
Sleep Mode Operation
The AD9744 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over
the specified supply range of 2.7 V to 3.6 V and temperature
range. This mode can be activated by applying a logic level 1 to
the SLEEP pin. The SLEEP pin logic threshold is equal to 0.5
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9744 remains enabled if this
input is left disconnected. The AD9744 takes less than 50 ns to
power down and approximately 5 s to power back up.
POWER DISSIPATION
several factors that include:
The power supply voltages (AVDD, CLKVDD, and
DVDD)
The full-scale current output IOUTFS
The update rate fCLOCK
The reconstructed digital input waveform
The power dissipation is directly proportional to the analog supply
current, IAVDD, and the digital supply current, IDVDD. IAVDD is
insensitive to fCLOCK. Conversely, IDVDD is dependent on both the
shows IDVDD as a function of full-scale sine wave output ratios
(fOUT/fCLOCK) for various update rates with DVDD = 3.3 V.
Figure 31. IAVDD vs. IOUTFS
Figure 32. IDVDD vs. Ratio at DVDD = 3.3 V
CLK+
TO DAC CORE
CLK–
VTT = 1.3V NOM
50
50
AD9744
CLOCK
RECEIVER
02913-026
–3
–2
2
–1
0
1
65
75
ns
dB
3
55
45
35
60
70
50
40
50MHz SFDR
20MHz SFDR
50MHz SFDR
02913-027
IOUTFS (mA)
35
0
2
I AVDD
(mA)
30
25
20
15
10
4
6
8
10
12
14
16
18
20
02913-028
RATIO (fOUT/fCLOCK)
20
0.01
1
0.1
I DVDD
(mA)
14
16
18
12
10
8
6
4
2
0
165MSPS
210MSPS
65MSPS
02913-029
125MSPS
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9744ARZRL1 | 制造商:AD 制造商全称:Analog Devices 功能描述:14-Bit, 210 MSPS TxDAC㈢ D/A Converter |
| AD9744-EB | 制造商:Analog Devices 功能描述:AD9744 EVALUATION BOARD (AD9744-EB) - Bulk |
| AD9745 | 制造商:AD 制造商全称:Analog Devices 功能描述:Dual 8-/10-/12-/14-/16-Bit 250 MSPS Digital-to-Analog Converters |
| AD9745BCPZ | 功能描述:IC DAC 2CH 12BIT 250MSPS 72LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 标准包装:1 系列:- 设置时间:4.5µs 位数:12 数据接口:串行，SPI? 转换器数目:1 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOICN 包装:剪切带 (CT) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:* 其它名称:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9745BCPZRL | 功能描述:IC DAC DUAL 12B 250MSPS 72-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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