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参数资料
| 型号： | AD9748ACP-PCBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/24页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9748ACP |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 8 |
| 采样率（每秒）： | 210M |
| 数据接口： | 并联 |
| 设置时间： | 11ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9748 |
| 相关产品： | AD9748ACPZ-ND - IC DAC 8BIT 210MSPS 32-LFCSP |
AD9748
Data Sheet
Rev. B | Page 14 of 24
DAC TIMING
Input Clock and Data Timing Relationship
Dynamic performance in a DAC is dependent on the
relationship between the position of the clock edges and the
time at which the input data changes. The AD9748 is rising
edge triggered, and so exhibits dynamic performance sensitivity
when the data transition is close to this edge. In general, the
goal when applying the AD9748 is to make the data transition
close to the falling clock edge. This becomes more important as
the sample rate increases. Figure 21 shows the relationship of
SFDR to clock placement with different sample rates. Note that
at the lower sample rates, more tolerance is allowed in clock
placement, while at higher rates, more care must be taken.
50MHz SFDR
20MHz SFDR
CLOCK PLACEMENT (ns)
SFDR
(dB)
80
65
70
75
55
60
35
40
45
50
30
0
2
6
4
8
10
12
03211-018
Figure 21. SFDR vs. Clock Placement @ fOUT = 20 MHz and 50 MHz
(fCLOCK = 165 MSPS)
Sleep Mode Operation
The AD9748 has a power-down function that turns off the output
current and reduces the supply current to less than 6 mA over the
specified supply range of 2.7 V to 3.6 V and the temperature range.
This mode can be activated by applying a Logic Level 1 to the
SLEEP pin. The SLEEP pin logic threshold is equal to 0.5
AVDD. This digital input also contains an active pull-down
circuit that ensures that the AD9748 remains enabled if this
input is left disconnected. The AD9748 takes less than 50 ns to
power down and approximately 5 s to power back up.
POWER DISSIPATION
several factors that include the:
Power supply voltages (AVDD, CLKVDD, and DVDD)
Full-scale current output (IOUTFS)
Update rate (fCLOCK)
Reconstructed digital input waveform
The power dissipation is directly proportional to the analog
supply current, IAVDD, and the digital supply current, IDVDD. IAVDD
insensitive to fCLOCK.
Conversely, IDVDD is dependent on both the digital input
as a function of full-scale sine wave output ratios (fOUT/fCLOCK)
for various update rates with DVDD = 3.3 V.
IOUTFS (mA)
35
0
2
I AVDD
(mA)
30
25
20
15
10
4
6
8
10
12
14
16
18
20
03211-019
Figure 22. IAVDD vs. IOUTFS
RATIO (fOUT/fCLOCK)
20
0.01
1
0.1
I DV
DD
(
mA)
14
16
18
12
10
8
6
4
2
0
165MSPS
210MSPS
65MSPS
032
1
1-
041
125MSPS
Figure 23. IDVDD vs. Ratio @ DVDD = 3.3 V
fCLOCK (MSPS)
I CLKVDD
(mA)
11
0
150
100
50
200
250
PECL
DIFF
SE
10
9
8
7
6
5
4
3
2
1
03211-042
Figure 24. ICLKVDD vs. fCLOCK and Clock Mode
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| AD9748ACPRL7 | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 8-bit 32-Pin LFCSP EP T/R |
| AD9748ACPZ | 功能描述:IC DAC 8BIT 210MSPS 32-LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 设置时间:4µs 位数:12 数据接口:串行 转换器数目:2 电压电源:单电源 功率耗散（最大）:- 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:8-TSSOP，8-MSOP（0.118"，3.00mm 宽） 供应商设备封装:8-uMAX 包装:管件 输出数目和类型:2 电压，单极 采样率（每秒）:* 产品目录页面:1398 (CN2011-ZH PDF) |
| AD9748ACPZ | 制造商:Analog Devices 功能描述:DAC, 8BIT, 210MSPS, LFCSP-32 |
| AD9748ACPZRL7 | 功能描述:IC DAC 8BIT 210MSPS 32LFCSP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 特色产品:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/°C Reference 标准包装:91 系列:- 设置时间:4µs 位数:10 数据接口:MICROWIRE?，串行，SPI? 转换器数目:8 电压电源:单电源 功率耗散（最大）:2.7mW 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:14-WFDFN 裸露焊盘 供应商设备封装:14-DFN-EP（4x3） 包装:管件 输出数目和类型:8 电压，单极 采样率（每秒）:* |
| AD9748XCP | 制造商:AD 制造商全称:Analog Devices 功能描述:8-Bit, 165 MSPS TxDAC D/A Converter |
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