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| 型号： | AD9751-EB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 2/28页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9751 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 10 |
| 采样率（每秒）： | 300M |
| 数据接口： | 并联 |
| 设置时间： | 11ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9751 |
| 相关产品： | AD9751ASTZRL-ND - IC DAC 10BIT 300MSPS 48LQFP AD9751ASTZ-ND - IC DAC 10BIT 300MSPS 48-LQFP |
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REV. C
AD9751
–10–
FUNCTIONAL DESCRIPTION
Figure 3 shows a simplified block diagram of the AD9751. The
AD9751 consists of a PMOS current source array capable of
providing up to 20 mA of full-scale current, IOUTFS. The array is
divided into 31 equal sources that make up the five most signifi-
cant bits (MSBs). The next four bits, or middle bits, consist of
15 equal current sources whose value is 1/16th of an MSB cur-
rent source. The remaining LSB is a binary weighted fraction of
the middle bit current sources. Implementing the middle and
lower bits with current sources, instead of an R-2R ladder,
enhances dynamic performance for multitone or low amplitude
signals and helps maintain the DAC’s high output impedance
(i.e., >100 k
).
All of the current sources are switched to one or the other of the
two outputs (i.e., IOUTA or IOUTB) via PMOS differential current
switches. The switches are based on a new architecture that
significantly improves distortion performance. This new switch
architecture reduces various timing errors and provides match-
ing complementary drive signals to the inputs of the differential
current switches.
The analog and digital sections of the AD9751 have separate
power supply inputs (i.e., AVDD and DVDD) that can operate
independently over a 3.0 V to 3.6 V range. The digital section,
which is capable of operating at a 300 MSPS clock rate, consists
of edge-triggered latches and segment decoding logic circuitry.
The analog section includes the PMOS current sources, the
associated differential switches, a 1.20 V band gap voltage refer-
ence, and a reference control amplifier.
The full-scale output current is regulated by the reference
control amplifier and can be set from 2 mA to 20 mA via an
external resistor, RSET. The external resistor, in combination
with both the reference control amplifier and voltage reference
VREFIO, sets the reference current IREF, which is replicated to the
segmented current sources with the proper scaling factor. The
full-scale current, IOUTFS, is 32 times the value of IREF.
REFERENCE OPERATION
The AD9751 contains an internal 1.20 V band gap reference.
This can easily be overdriven by an external reference with no
effect on performance. REFIO serves as either an input or output,
depending on whether the internal or an external reference is
used. To use the internal reference, simply decouple the REFIO
pin to ACOM with a 0.1
F capacitor. The internal reference
voltage will be present at REFIO. If the voltage at REFIO is to
be used elsewhere in the circuit, an external buffer amplifier with
an input bias current less than 100 nA should be used. An example
of the use of the internal reference is shown in Figure 4.
A low impedance external reference can be applied to REFIO,
as shown in Figure 5. The external reference may provide either
a fixed reference voltage to enhance accuracy and drift perfor-
mance or a varying reference voltage for gain control. Note that
the 0.1
F compensation capacitor is not required since the inter-
nal reference is overdriven, and the relatively high input impedance
of REFIO minimizes any loading of the external reference.
REFERENCE CONTROL AMPLIFIER
The AD9751 also contains an internal control amplifier that is
used to regulate the DAC’s full-scale output current, IOUTFS.
The control amplifier is configured as a voltage-to-current con-
verter as shown in Figure 4, so that its current output, IREF, is
determined by the ratio of VREFIO and an external resistor, RSET,
as stated in Equation 4. IREF is applied to the segmented current
sources with the proper scaling factor to set IOUTFS as stated in
Equation 3.
The control amplifier allows a wide (10:1) adjustment span of
IOUTFS over a 2 mA to 20 mA range by setting IREF between
62.5
A and 625 A. The wide adjustment span of IOUTFS provides
several application benefits. The first benefit relates directly to
the power dissipation of the AD9751, which is proportional to
IOUTFS (refer to the Power Dissipation section). The second
benefit relates to the 20 dB adjustment, which is useful for sys-
tem gain control purposes.
The small signal bandwidth of the reference control amplifier is
approximately 500 kHz and can be used for low frequency, small
signal multiplying applications.
AD9751
IOUTA
IOUTB
SEGMENTED
SWITCHES FOR
DB0 TO DB9
DAC
FSADJ
REFIO
1.2V REF
DIV0
PLLLOCK
DIGITAL DATA INPUTS
0.1 F
RSET
2k
RLOAD
50
DB0 – DB9
DCOM
PMOS CURRENT
SOURCE ARRAY
AVDD
3.0V TO 3.6V
DVDD
2–1 MUX
PORT 1 LATCH
DAC LATCH
ACOM
PORT 2 LATCH
DIV1
PLL
CIRCUITRY
PLLVDD
CLKVDD
CLK+
CLK–
CLKCOM
RESET
LPF
DB0 – DB9
VOUTB
RLOAD
50
VOUTA
VDIFF = VOUTA – VOUTB
Figure 3. Simplified Block Diagram
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9752 | 制造商:AD 制造商全称:Analog Devices 功能描述:12-Bit, 125 MSPS High Performance TxDAC D/A Converter |
| AD9752AR | 功能描述:IC DAC 12BIT 125MSPS 28-SOIC RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
| AD9752ARRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 12-bit 28-Pin SOIC W T/R 制造商:Rochester Electronics LLC 功能描述:12-BIT 125 MSPS+ TXDAC D/A CONVERTER - Tape and Reel |
| AD9752ARU | 功能描述:IC DAC 12BIT 125MSPS HP 28-TSSOP RoHS:否 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:TxDAC® 产品培训模块:Data Converter Fundamentals DAC Architectures 标准包装:750 系列:- 设置时间:7µs 位数:16 数据接口:并联 转换器数目:1 电压电源:双 ± 功率耗散（最大）:100mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:28-LCC（J 形引线） 供应商设备封装:28-PLCC（11.51x11.51） 包装:带卷 (TR) 输出数目和类型:1 电压，单极；1 电压，双极 采样率（每秒）:143k |
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