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参数资料
| 型号： | AD9764-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/22页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9764 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 设置时间： | 35ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9764 |
REV. B
–2–
AD9764–SPECIFICATIONS
DC SPECIFICATIONS
Parameter
Min
Typ
Max
Units
RESOLUTION
14
Bits
DC ACCURACY
1
Integral Linearity Error (INL)
TA = +25
°C
–4.5
±2.5
+4.5
LSB
TMIN to TMAX
–6.5
+6.5
LSB
Differential Nonlinearity (DNL)
TA = +25
°C
–2.5
±1.5
+2.5
LSB
TMIN to TMAX
–4.5
+4.5
LSB
ANALOG OUTPUT
Offset Error
–0.025
+0.025
% of FSR
Gain Error (Without Internal Reference)
–2
±1
+2
% of FSR
Gain Error (With Internal Reference)
–7
±1
+7
% of FSR
Full-Scale Output Current2
2.0
20.0
mA
Output Compliance Range
–1.0
1.25
V
Output Resistance
100
k
Output Capacitance
5
pF
REFERENCE OUTPUT
Reference Voltage
1.08
1.20
1.32
V
Reference Output Current3
100
nA
REFERENCE INPUT
Input Compliance Range
0.1
1.25
V
Reference Input Resistance
1
M
Small Signal Bandwidth (w/o CCOMP1)
4
1.4
MHz
TEMPERATURE COEFFICIENTS
Offset Drift
0
ppm of FSR/
°C
Gain Drift (Without Internal Reference)
±50
ppm of FSR/
°C
Gain Drift (With Internal Reference)
±100
ppm of FSR/
°C
Reference Voltage Drift
±50
ppm/
°C
POWER SUPPLY
Supply Voltages
AVDD5
2.7
5.0
5.5
V
DVDD
2.7
5.0
5.5
V
Analog Supply Current (IAVDD)25
30
mA
Digital Supply Current (IDVDD)
6
1.5
4
mA
Supply Current Sleep Mode (IAVDD)
5.0
8.5
mA
Power Dissipation6 (5 V, IOUTFS = 20 mA)
133
170
mW
Power Dissipation7 (5 V, IOUTFS = 20 mA)
190
mW
Power Dissipation7 (3 V, IOUTFS = 2 mA)
45
mW
Power Supply Rejection Ratio8—AVDD
–0.4
+0.4
% of FSR/V
Power Supply Rejection Ratio8—DVDD
–0.025
+0.025
% of FSR/V
OPERATING RANGE
–40
+85
°C
NOTES
1Measured at I
OUTA, driving a virtual ground.
2Nominal full-scale current, I
OUTFS, is 32 × the I REF current.
3Use an external buffer amplifier to drive any external load.
4Reference bandwidth is a function of external cap at COMP1 pin and signal level.
5For operation below 3 V, it is recommended that the output current be reduced to 12 mA or less to maintain optimum performance.
6Measured at f
CLOCK = 25 MSPS and fOUT = 1.0 MHz.
7Measured as unbuffered voltage output with I
OUTFS = 20 mA and 50 RLOAD at IOUTA and IOUTB, fCLOCK = 100 MSPS and fOUT = 40 MHz.
8
± 5% Power supply variation.
Specifications subject to change without notice.
(TMIN to TMAX , AVDD = +5 V, DVDD = +5 V, IOUTFS = 20 mA, unless otherwise noted)
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